Datasheet

134
2467X–AVR–06/11
ATmega128
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 61. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 123.)
Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Table 61. Waveform Generation Mode Bit Description
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter Mode of
Operation
(1)
TOP
Update of
OCRnx at
TOVn Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
10 0 0 1PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
20 0 1 0PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
30 0 1 1PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
50 1 0 1Fast PWM, 8-bit 0x00FF BOTTOM TOP
60 1 1 0Fast PWM, 9-bit 0x01FF BOTTOM TOP
70 1 1 1Fast PWM, 10-bit 0x03FF BOTTOM TOP
81 0 0 0PWM, Phase and Frequency
Correct
ICRn BOTTOM BOTTOM
91 0 0 1PWM, Phase and Frequency
Correct
OCRnA BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWMICRnBOTTOMTOP
15 1 1 1 1 Fast PWMOCRnABOTTOMTOP