Features • High-performance, Low-power Atmel®AVR®8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 128Kbytes of In-System Self-programmable Flash program memory – 4Kbytes EEPROM – 4Kbytes Internal SRAM – Write/Erase
ATmega128 Pin Configurations 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1(RD) PG0(WR) (OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7 PEN RXD0/(PDI) PE0 (TXD0/P
ATmega128 Block Diagram PC0 - PC7 RESET PA0 - PA7 XTAL1 PF0 - PF7 XTAL2 Figure 2. Block Diagram VCC GND PORTA DRIVERS PORTF DRIVERS DATA DIR. REG. PORTF DATA REGISTER PORTF PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC CALIB.
ATmega128 The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega128 The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128. ATmega103 Compatibility Mode By programming the M103C fuse, the Atmel ® ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above.
ATmega128 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega128 In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running.
ATmega128 Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: 1. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device.
ATmega128 AVR CPU Core Introduction This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals and handle interrupts. Architectural Overview Figure 3.
ATmega128 Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection.
ATmega128 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
ATmega128 Figure 4. AVR CPU General Purpose Working Registers 7 0 Addr.
ATmega128 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.
ATmega128 Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6.
ATmega128 There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.
ATmega128 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega128 AVR ATmega128 Memories This section describes the different memories in the Atmel® AVR® ATmega128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega128 contains 128Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega128 SRAM Data Memory The Atmel® AVR® ATmega128 supports two different configurations for the SRAM data memory as listed in Table 1. Table 1. Memory Configurations Configuration Internal SRAM Data Memory External SRAM Data Memory Normal mode 4096 up to 64K ATmega103 Compatibility mode 4000 up to 64K Figure 9 shows how the ATmega128 SRAM Memory is organized.
ATmega128 The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 4096bytes of internal data SRAM in the ATmega128 are all accessible through all these addressing modes.
ATmega128 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory access instruction EEPROM Data Memory Next instruction The Atmel® AVR®ATmega128 contains 4Kbytes of data EEPROM memory.
ATmega128 • Bits 11..0 – EEAR11..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 4 Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. EEPROM Data Register – EEDR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7..0 – EEDR7.
ATmega128 The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 273 for details about boot programming.
ATmega128 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega128 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega128 ation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. I/O Memory The I/O space definition of the ATmega128 is shown in “Register Summary” on page 362. All Atmel® AVR®ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
ATmega128 Figure 11. External Memory with Sector Select Memory Configuration B Memory Configuration A 0x0000 0x0000 Internal memory Internal memory 0x0FFF 0x1000 0x10FF 0x1100 Lower sector SRW01 SRW00 SRW10 SRL[2..
ATmega128 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB. When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “I/O Ports” on page 65.
ATmega128 Pull-up and Buskeeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 32.
ATmega128 Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address Data Write XX WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega128 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data XX Write Address Data WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega128 • Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.
ATmega128 External Memory Control Register B – XMCRB Bit 7 6 5 4 3 2 1 0 XMBK – – – – XMM2 XMM1 XMM0 Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 XMCRB • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the bus keeper.
ATmega128 addresses 0x8000 to 0x8FFF. To the Application software, the external 32 Kbyte memory will appear as one linear 32 Kbyte address space from 0x1000 to 0x8FFF. Figure 17.
ATmega128 Using all 64 Kbyte Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only 60 Kbyte of External Memory is available by default (address space 0x0000 to 0x10FF is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address.
ATmega128 System Clock and Clock Options Clock Systems and their Distribution Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 44. The clock systems are detailed below. Figure 18.
ATmega128 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
ATmega128 Note: 1. For all fuses “1” means unprogrammed while “0” means programmed. The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation.
ATmega128 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz crystal or a ceramic resonator may be used. The CKOPT fuse selects between two different Oscillator Amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full railto-rail swing on the output.
ATmega128 Table 9. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 0 0 0 0 1 1 1 1 Notes: Low-frequency Crystal Oscillator SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 (1) 258 CK 4.1ms Ceramic resonator, fast rising power 01 258 CK(1) 65ms Ceramic resonator, slowly rising power 10 1K CK(2) – Ceramic resonator, BOD enabled 11 1K CK(2) 4.
ATmega128 External RC Oscillator For timing insensitive applications, the External RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the CKOPT fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor.
ATmega128 Calibrated Internal The Calibrated Internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by RC Oscillator programming the CKSEL fuses as shown in Table 13. If selected, it will operate with no external components. The CKOPT fuse should always be unprogrammed when using this clock option.
ATmega128 to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0MHz, 2.0MHz, 4.0MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 15. Table 15. Internal RC Oscillator Frequency Range.
ATmega128 Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36pF.
ATmega128 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega128 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega128 Standby Mode When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles. Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode.
ATmega128 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
ATmega128 JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCSR.
ATmega128 System Control and Reset Resetting the AVR During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
ATmega128 Figure 22. Reset Logic DATA BUS D Q L Q MCU Control and Status Register (MCUCSR) PORF BORF EXTRF WDRF JTRF PEN Pull-up Resistor Power-On Reset Circuit Brown-Out Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE FILTER JTAG Reset Register Reset Circuit COUNTER RESET RESET Watchdog Timer Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 19.
ATmega128 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1for ATmega128L and BODLEVEL=0 for ATmega128.
ATmega128 Figure 25. External Reset During Operation CC Brown-out Detection ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection.
ATmega128 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 54 for details on operation of the Watchdog Timer. Figure 27. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU reset.
ATmega128 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 20. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODEN fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled.
ATmega128 Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON. Safety Level WDT Initial State How to Disable the WDT How to Change Time-out M103C WDTON Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed sequence Unprogrammed Programmed 2 Enabled Always enabled Timed sequence Programmed Unprogrammed 0 Disabled Timed sequence No restriction Programmed Programmed 2 Enabled Always enabled Timed sequence Figure 28.
ATmega128 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 57. • Bits 2..
ATmega128 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega128 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
ATmega128 Interrupts Interrupt Vectors in ATmega128 This section describes the specifics of the interrupt handling as performed in Atmel® AVR® ATmega128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 14. Table 23. Reset and Interrupt Vectors Vector No.
ATmega128 Table 23. Reset and Interrupt Vectors Vector No. Program Address(2) 31 Source Interrupt Definition $003C(3) USART1, RX USART1, Rx Complete 32 $003E(3) USART1, UDRE USART1 Data Register Empty 33 (3) USART1, TX USART1, Tx Complete (3) $0040 34 $0042 TWI Two-wire Serial Interface 35 $0044(3) SPM READY Store Program Memory Ready Notes: 1.
ATmega128 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode Comments $0000 jmp RESET ; Reset Handler $0002 jmp EXT_INT0 ; IRQ0 Handler $0004 jmp EXT_INT1 ; IRQ1 Handler $0006 jmp EXT_INT2 ; IRQ2 Handler $0008 jmp EXT_INT3 ; IRQ3 Handler $000A jmp EXT_INT4 ; IRQ4 Handler $000C jmp EXT_INT5 ; IRQ5 Handler $000E jmp EXT_INT6 ; IRQ6 Handler $0010 jmp EXT_INT7 ; IRQ7 Handler $0012 jmp TIM2_COMP ; Tim
ATmega128 When the BOOTRST fuse is unprogrammed, the Boot section size set to 8Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address LabelsCode $0000 Comments RESET:ldi r16,high(RAMEND); Main program start $0001 out SPH,r16 $0002 ldi r16,low(RAMEND) ; Set stack pointer to top of RAM $0003 $0004 out sei SPL,r16 $0005 ; Enable interrupts xxx ; .
ATmega128 Moving Interrupts Between Application and Boot Space MCU Control Register – MCUCR $F049 $F04A out sei SPL,r16 $F04B ; Enable interrupts xxx The General Interrupt Control Register controls the placement of the interrupt vector table.
ATmega128 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
ATmega128 I/O Ports Introduction All Atmel® AVR® ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega128 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O port pin, here generically called Pxn. Figure 30.
ATmega128 low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem.
ATmega128 shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 32.
ATmega128 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega128 Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega128 Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 33 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 26. Generic Description of Overriding Signals for Alternate Functions. Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega128 Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 TSM – – – ACME PUD PSR0 PSR321 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 66 for more details about this feature.
ATmega128 Table 29. Overriding Signals for Alternate Functions in PA3..
ATmega128 • OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • OC1A, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A.
ATmega128 Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/OC2/OC1C PB6/OC1B PB5/OC1A PB4/OC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 (1) PVOE OC2/OC1C ENABLE OC1B ENABLE OC1A ENABLE OC0 ENABLE PVOV OC2/OC1C(1) OC1B OC1A OC0B DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – – – – – AIO Note: 1. See “Output Compare Modulator (OCM1C2)” on page 160 for details. OC1C does not exist in ATmega103 compatibility mode.
ATmega128 Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. The Port C has an alternate function as the address high byte for the External Memory Interface. Table 33.
ATmega128 Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1) Signal Name PC3/A11 PC2/A10 PC1/A9 PC0/A8 PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV 0 0 0 0 DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) DDOV 1 1 1 1 PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PVOV A11 A10 A9 A8 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: Alternate Functions of Port D 1.
ATmega128 • ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2.
ATmega128 Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T2 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 UMSEL1 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T2 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 38. Overriding Signals for Alternate Functions in PD3..
ATmega128 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39. Table 39.
ATmega128 XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega128. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input.
ATmega128 Table 41. Overriding Signals for Alternate Functions in PE3..
ATmega128 TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 – Port F, Bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 – ADC0 – Port F, Bit 3..0 Analog to Digital Converter, Channel 3..0. Table 43.
ATmega128 Alternate Functions of Port G In Atmel® AVR®ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows: Table 45.
ATmega128 Table 47.
ATmega128 Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Bit 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 PINA7
ATmega128 Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINC In Atmel® AVR®ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not running.
ATmega128 Port F Data Direction Register – DDRF Port F Input Pins Address – PINF Bit 7 6 5 4 3 2 1 0 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A DDRF PINF Note that PORTF and DDRF Registers are not available in Atmel® AVR®ATmega
ATmega128 External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4).
ATmega128 Table 48. Interrupt Sense Control(1) ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Reserved 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: Description 1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register.
ATmega128 External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
ATmega128 8-bit Timer/Counter0 with PWM and Asynchronous Operation Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module.
ATmega128 tive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 94. for details.
ATmega128 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. top Signalizes that TCNT0 has reached maximum value. bottom Signalizes that TCNT0 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATmega128 Figure 36. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
ATmega128 (FOC0) strobe bit in normal mode. The OC0 Register keeps its value even when changing between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The waveform generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match.
ATmega128 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega128 value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to Toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output.
ATmega128 Figure 39. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter overflow flag (TOV0) is set each time the counter reaches Max If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin.
ATmega128 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the output compare (OC0) is cleared on the compare match between TCNT0 and OCR0 while counting up, and set on the compare match while downcounting.
ATmega128 PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega128 Figure 42. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
ATmega128 Figure 44.
ATmega128 Table 52. Waveform Generation Mode Bit Description Mode WGM01(1) (CTC0) WGM00(1) (PWM0) 0 0 1 Timer/Counter Mode of Operation TOP Update of OCR0 at TOV0 Flag Set on 0 Normal 0xFF Immediate MAX 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
ATmega128 Table 55. Compare Output Mode, Phase Correct PWM Mode(1) COM01 COM00 0 0 Normal port operation, OC0 disconnected. 0 1 Reserved 1 0 Clear OC0 on compare match when up-counting. Set OC0 on compare match when downcounting. 1 1 Set OC0 on compare match when up-counting. Clear OC0 on compare match when downcounting. Note: Description 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP.
ATmega128 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – – AS0 TCN0UB OCR0UB TCR0UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O. When AS0 is written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
ATmega128 • When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the Temporary Register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress.
ATmega128 • Timer/Counter Interrupt Mask Register – TIMSK During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock.
ATmega128 Figure 45. Prescaler for Timer/Counter0 clkT0S PSR0 clkT0S/1024 clkT0S/256 clkT0S/8 AS0 clkT0S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT0S/64 clkI/O clkT0S/32 Timer/Counter Prescaler 0 CS00 CS01 CS02 TIMER/COUNTER0 CLOCK SOURCE clkT0 The clock source for Timer/Counter0 is named clkT0. clkT0 is by default connected to the main system clock clkI/O. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1 pin.
ATmega128 • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set.
ATmega128 16-bit Timer/Counter (Timer/Counter 1 and Timer/Counter3 ) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATmega128 Figure 46. 16-bit Timer/Counter Block Diagram Count Clear Direction TOVx (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTx Tx = =0 OCFxA (Int.Req.) Waveform Generation = OCxA OCRxA OCFxB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCxB OCRxB OCFxC (Int.Req.) Waveform Generation = OCRxC OCxC ( From Analog Comparator Ouput ) ICFx (Int.Req.
ATmega128 See “Output Compare Units” on page 120.. The compare match event will also set the compare match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 227.
ATmega128 Accessing 16-bit Registers The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16bit access. The same Temporary Register is shared between all 16-bit registers within each 16bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega128 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega128 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega128 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 143.
ATmega128 are generated on the output compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 123. The Timer/Counter Overflow (TOVn) flag is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega128 into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register.
ATmega128 Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the output compare flag generates an output compare interrupt. The OCFnx flag is automatically cleared when the interrupt is executed.
ATmega128 The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx buffer register, and if double buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (buffer or compare) register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNTn- and ICRn Register). Therefore OCRnx is not read via the high byte Temporary Register (TEMP).
ATmega128 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega128 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega128 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
ATmega128 Figure 52. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
ATmega128 The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N ⋅ ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
ATmega128 Figure 53. Phase Correct PWM Mode, Timing Diagram OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
ATmega128 the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 ⋅ N ⋅ TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega128 Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
ATmega128 The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA Output will toggle with a 50% duty cycle.
ATmega128 Figure 57 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at BOTTOM. Figure 57.
ATmega128 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A
ATmega128 Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode Table 59. Compare Output Mode, Fast PWM COMnA1/COMnB1/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected.
ATmega128 • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 61. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 123.) Table 61.
ATmega128 Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B TCCR3B • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (
ATmega128 Table 62. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on Tn pin. Clock on falling edge 1 1 1 External clock source on Tn pin.
ATmega128 Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] Timer/Counter3 – TCNT3H and TCNT3L TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read an
ATmega128 Output Compare Register 3 B – OCR3BH and OCR3BL Bit 7 6 5 4 3 2 1 0 OCR3B[15:8] OCR3BH OCR3B[7:0] Output Compare Register 3 C – OCR3CH and OCR3CL OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR3C[15:8] OCR3CH OCR3C[7:0] OCR3CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared
ATmega128 • Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt vector (See “Interrupts” on page 59.) is executed when the ICF1 flag, located in TIFR, is set.
ATmega128 • Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector (See “Interrupts” on page 59) is executed when the TOV3 flag, located in ETIFR, is set.
ATmega128 TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Extended Timer/Counter Interrupt Flag Register – ETIFR Bit 7 6 5 4 3 2 1 0 – – ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ETIFR • Bit 7:6 – Reserved Bits These bits are reserved for future use.
ATmega128 Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.
ATmega128 Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all of the mentioned Timer/Counters. Internal Clock Source The Timer/Counter can be clocked directly by the System Clock (by setting the CSn2:0 = 1).
ATmega128 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
ATmega128 8-bit Timer/Counter2 with PWM Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 61.
ATmega128 The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare Unit” on page 147. for details. The compare match event will also set the compare flag (OCF2) which can be used to generate an output compare interrupt request.
ATmega128 bottom Signalize that TCNT2 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not.
ATmega128 ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly.
ATmega128 Figure 64. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator D Q 1 OCn DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the output compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega128 overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the timer resolution can be increased by software.
ATmega128 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM.
ATmega128 The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = ----------------N ⋅ 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
ATmega128 Figure 67. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
ATmega128 • Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clkT2) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 68 contains timing data for basic Timer/Counter operation.
ATmega128 Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 71.
ATmega128 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode.
ATmega128 Table 65. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on compare match 1 0 Clear OC2 on compare match 1 1 Set OC2 on compare match Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 66. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected.
ATmega128 Table 68. Clock Select Bit Description CS22 CS21 CS20 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T2 pin. Clock on falling edge 1 1 1 External clock source on T2 pin. Clock on rising edge If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
ATmega128 Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega128 Output Compare Modulator (OCM1C2) Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 111 and “8-bit Timer/Counter2 with PWM” on page 145.
ATmega128 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. Timing Example Figure 74 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 74.
ATmega128 Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel AVR ATmega128 and peripheral devices or between several AVR devices.
ATmega128 When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the 8 bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
ATmega128 Note: 1. See “Alternate Functions of Port B” on page 73 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins.
ATmega128 The following code examples show how to initialize the SPI as a slave and how to perform a simple reception.
ATmega128 SS Pin Functionality Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega128 and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summarized below: Table 70.
ATmega128 SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
ATmega128 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 70 and Table 71, as done below: Table 73.
ATmega128 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
ATmega128 Figure 79. USART Block Diagram Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATABUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC Refer to Figure 1 on page 2, Table 36 on page 77, and Table 39 on page 80 for USART pin placement.
ATmega128 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second buffer register has been added. The two buffer registers operate as a circular FIFO buffer.
ATmega128 Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
ATmega128 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 80 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver.
ATmega128 Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit.
ATmega128 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization.
ATmega128 Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid– The USART den by the USART and given the function as the transmitter’s serial output. The baud rate, mode Transmitter of operation and frame format must be set up once before doing any transmissions.
ATmega128 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9 bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16.
ATmega128 transmission is used, the data register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the data register empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
ATmega128 The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used.
ATmega128 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and UPE bits, which all are stored in the FIFO, will change.
ATmega128 Note: Receive Compete Flag and Interrupt 1. See “About Code Examples” on page 8. The receive function example reads all the I/O registers into the register file before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
ATmega128 Parity Checker The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATmega128 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 83 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for normal mode, and 8 times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the double speed mode (U2X = 1) of operation.
ATmega128 Figure 85. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
ATmega128 Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow % Rfast % Max Total Error % Recommended Max Receiver Error % 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 76.
ATmega128 The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7).
ATmega128 USART Register Description USARTn I/O Data Register – UDRn Bit 7 6 5 4 3 2 1 0 RXBn[7:0] UDRn (Read) TXBn[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDRn Register location.
ATmega128 This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega128 Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxDn port.
ATmega128 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBSn Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bits • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (character size) in a frame the Receiver and Transmitter use. Table 80.
ATmega128 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn baud rate.
ATmega128 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 82. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega128 Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.
ATmega128 Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
ATmega128 Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 16.0000MHz Baud Rate (bps) UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 4800 207 0.2% 416 -0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 -0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 -0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 -0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 -3.5% 16 2.1% 230.4k 3 8.5% 8 -3.5% 250k 3 0.0% 7 0.0% 0.5M 1 0.0% 3 0.
ATmega128 Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega128 high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 322.
ATmega128 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.
ATmega128 Figure 90. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 SLA+R/W Combining Address and Data Packets Into a Transmission STOP, REPEATED START or Next Data Byte Data Byte A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal.
ATmega128 The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the master with the shortest high period. The low period of the combined clock is equal to the low period of the master with the longest low period.
ATmega128 Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets.
ATmega128 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 94. All registers drawn in a thick line are accessible through the AVR data bus. Figure 94.
ATmega128 or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a master.
ATmega128 TWI Register Description TWI Bit Rate Register – TWBR Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR • Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
ATmega128 • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
ATmega128 TWI Data Register – TWDR Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware.
ATmega128 abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. Application Action Figure 95. Interfacing the Application to the TWI in a Typical Transmission TWI bus 1. Application writes to TWCR to initiate transmission of START 3. Check TWSR to see if START was sent.
ATmega128 application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
ATmega128 Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared. • When the TWINT flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle.
ATmega128 Assembly Code Example 1 ldi r16, (1<
ATmega128 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega128 Figure 96. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ R1 Device n R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag.
ATmega128 After a repeated START condition (state $10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 88.
ATmega128 Figure 97.
ATmega128 Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see Figure 98). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega128 enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Figure 99.
ATmega128 Table 89.
ATmega128 The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address.
ATmega128 Table 90.
ATmega128 Figure 101. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega128 TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
ATmega128 Table 91.
ATmega128 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 92. Status $F8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
ATmega128 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 105.
ATmega128 Figure 106.
ATmega128 Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega128 disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 53.
ATmega128 94. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 94. Analog Comparator Multiplexed Input ACME ADEN MUX2..
ATmega128 Analog to Digital Converter Features • • • • • • • • • • • • • • 10-bit Resolution 0.5LSB Integral Non-linearity ±2LSB Absolute Accuracy 13 - 260µs Conversion Time Up to 76.9kSPS (Up to 15 kSPS at Maximum Resolution) 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega128 Figure 108. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS0 ADPS2 ADPS1 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX4 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS PRESCALER AVCC GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC INTERNAL 2.
ATmega128 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 SB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
ATmega128 Prescaling and Figure 109. ADC Prescaler Conversion Timing ADEN Reset 7-BIT ADC PRESCALER CK/64 CK/128 CK/32 CK/16 CK/8 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
ATmega128 Figure 110. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 13 12 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample &Hold MUX and REFS Update Figure 111.
ATmega128 Table 95. ADC Conversion Time Condition Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 1.5/2.5 13/14 Normal conversions, differential Differential Gain Channels Sample & Hold (Cycles from Start of Conversion) When using differential gain channels, certain aspects of the conversion need to be taken into consideration. Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock.
ATmega128 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega128 sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result. Analog Input Circuitry The Analog Input circuitry for single ended channels is illustrated in Figure 113. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC.
ATmega128 Figure 114. ADC Power Connections (AD0) PA0 VCC GND 10µH 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 GND 63 AVCC 64 1 PEN 100nF 51 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible.
ATmega128 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB). Ideal value: 0LSB. Figure 115.
ATmega128 Figure 117. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB. Figure 118.
ATmega128 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 97 on page 242 and Table 98 on page 243). 0x000 represents ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega128 Table 96. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 1/512 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 511/512 VREF /GAIN 0x201 -511 VADCm - VREF /GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.
ATmega128 conversions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on page 245. • Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 98 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 98.
ATmega128 Table 98. Input Channel and Gain Selections (Continued) MUX4..0 Single Ended Input 11101 11110 1.23V (VBG) 11111 0V (GND) Note: ADC Control and Status Register A – ADCSRA Positive Differential Input Negative Differential Input Gain ADC5 ADC2 1x N/A 1. Can be used for offset calibration.
ATmega128 Table 99.
ATmega128 JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega128 The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
ATmega128 Figure 121. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundaryscan circuitry, JTAG programming circuitry, or On-chip Debug system.
ATmega128 on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The ExitIR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
ATmega128 A debugger, like the Atmel® AVR Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 250. The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work.
ATmega128 On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 MSB/IDRD 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega128 IEEE 1149.1 (JTAG) Boundaryscan Features • • • • • System Overview The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
ATmega128 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 122 shows the structure of the Device Identification Register. Figure 122.
ATmega128 Figure 123. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal Reset ClockDR · AVR_RESET Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 255 for a complete description.
ATmega128 SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latched are not connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states are: AVR_RESET; $C • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
ATmega128 Scanning the Digital Port Pins Figure 124 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.
ATmega128 Figure 125.
ATmega128 Figure 126. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn TWIEN Pxn SRC Slew-rate limited IDxn Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 127 is inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV. Figure 127.
ATmega128 Figure 128. Boundary-scan Cells for Oscillators and Clock Options XTAL1/TOSC1 To Next Cell ShiftDR Oscillator EXTEST From Digital Logic XTAL2/TOSC2 0 ENABLE ShiftDR To System Logic OUTPUT 1 FF1 0 D Q D Q 0 1 D G From Previous Cell ClockDR To next cell Q 1 UpdateDR From Previous Cell ClockDR Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator. Table 102.
ATmega128 Figure 129. Analog comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 130.
ATmega128 Table 103.
ATmega128 Table 104.
ATmega128 Table 104.
ATmega128 The Atmel® AVR® ADC is based on the analog circuitry shown in Figure 131 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits.
ATmega128 Table 105. Algorithm for Using the ADC PA3. ADCEN DAC MUXEN HOLD PRECH PA3. Data 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 1 0x200 0x08 1 1 0 0 0 Step 11 Actions Verify the COMP bit scanned out to be 1 PA3. Control Pullup_ Enable Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency.
ATmega128 ATmega128 Boundary-scan Order Table 106 shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
ATmega128 Table 106. ATmega128 Boundary-scan Order (Continued) Bit Number Signal Name Module 175 MUXEN_6 ADC 174 MUXEN_5 173 MUXEN_4 172 MUXEN_3 171 MUXEN_2 170 MUXEN_1 169 MUXEN_0 168 NEGSEL_2 167 NEGSEL_1 166 NEGSEL_0 165 PASSEN 164 PRECH 163 SCTEST 162 ST 161 VCCREN 160 PEN Programming enable (observe only) 159 PE0.Data Port E 158 PE0.Control 157 PE0.Pullup_Enable 156 PE1.Data 155 PE1.Control 154 PE1.Pullup_Enable 153 PE2.Data 152 PE2.
ATmega128 Table 106. ATmega128 Boundary-scan Order (Continued) Bit Number Signal Name Module 139 PE6.Pullup_Enable Port E 138 PE7.Data 137 PE7.Control 136 PE7.Pullup_Enable 135 PB0.Data 134 PB0.Control 133 PB0.Pullup_Enable 132 PB1.Data 131 PB1.Control 130 PB1.Pullup_Enable 129 PB2.Data 128 PB2.Control 127 PB2.Pullup_Enable 126 PB3.Data 125 PB3.Control 124 PB3.Pullup_Enable 123 PB4.Data 122 PB4.Control 121 PB4.Pullup_Enable 120 PB5.Data 119 PB5.Control 118 PB5.
ATmega128 Table 106. ATmega128 Boundary-scan Order (Continued) Bit Number Signal Name Module 103 RSTT 102 RSTHV Reset Logic (Observe-only) 101 EXTCLKEN Enable signals for main Clock/Oscillators 100 OSCON 99 RCOSCEN 98 OSC32EN 97 EXTCLK (XTAL1) 96 OSCCK 95 RCCK 94 OSC32CK 93 TWIEN TWI 92 PD0.Data Port D 91 PD0.Control 90 PD0.Pullup_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.
ATmega128 Table 106. ATmega128 Boundary-scan Order (Continued) Bit Number Signal Name Module 67 PG0.Control Port G 66 PG0.Pullup_Enable 65 PG1.Data 64 PG1.Control 63 PG1.Pullup_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pullup_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pullup_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pullup_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pullup_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.
ATmega128 Table 106. ATmega128 Boundary-scan Order (Continued) Bit Number Signal Name Module 31 PA6.Control Port A 30 PA6.Pullup_Enable 29 PA5.Data 28 PA5.Control 27 PA5.Pullup_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pullup_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pullup_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pullup_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pullup_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pullup_Enable 11 PF3.Data 10 PF3.Control 9 PF3.
ATmega128 Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description.
ATmega128 Boot Loader Support – ReadWhile-Write SelfProgramming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega128 section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. Read-While-Write Section – RWW If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read.
ATmega128 Figure 133.
ATmega128 Table 108. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega128 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega128 or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. • Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a special meaning, see description above.
ATmega128 Figure 134. Addressing the Flash During SPM(1) BIT 15 ZPCMSB RAMPZ ZPAGEMSB 1 0 0 PCMSB PROGRAM COUNTER Z - REGISTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE PCWORD WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: Self-Programming the Flash 1. The different variables used in Figure 134 are listed in Table 114 on page 285. 2. PCPAGE and PCWORD are listed in Table 124 on page 291.
ATmega128 Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) To execute page erase, set up the address in the Z-pointer and RAMPZ, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this operation. • Page Erase to the RWW section: The NRWW section can be read during the page erase.
ATmega128 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega128 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied.
ATmega128 ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB);init loop variable ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcsrval, (1<
ATmega128 Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence sts SPMCSR, spmcsrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret ATmega128 Boot Loader Parameters In Table 112 through Table 114, the parameters used in the description of the self programming are given. Table 112.
ATmega128 Table 114. Explanation of Different Variables Used in Figure 134 and the Mapping to the ZPointer(3) Corresponding Z-value Variable PCMSB 15 Most significant bit in the program counter. (The program counter is 16 bits PC[15:0]) 6 Most significant bit which is used to address the words within one page (128 words in a page requires 7 bits PC [6:0]). PAGEMSB Z16(1) Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega128 Memory Programming Program and Data Memory Lock Bits The Atmel® AVR®ATmega128 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 116. The Lock bits can only be erased to “1” with the Chip Erase command. Table 115.
ATmega128 Table 116. Lock Bit Protection Modes (Continued) Memory Lock Bits Protection Type 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega128 Table 118. Fuse High Byte Fuse High Byte Bit No. Description Default Value (4) OCDEN 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega128 the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on power-up in normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For theAtmel® AVR® ATmega128 the signature bytes are: 1. $000: $1E (indicates manufactured by Atmel) 2.
ATmega128 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the Atmel® AVR®ATmega128. Pulses are assumed to be at least 250ns unless otherwise noted. Signal Names In this section, some pins of the ATmega128 are referenced by signal names describing their functionality during parallel programming, see Figure 135 and Table 120.
ATmega128 Table 120. Pin Name Mapping (Continued) Signal Name in Programming Mode PAGEL BS2 DATA Pin Name I/O Function PD7 I Program Memory and EEPROM data Page Load PA0 I Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte) PB7-0 I/O Bi-directional Data bus (Output when OE is low) Table 121. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 122.
ATmega128 Table 125. No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB 4 Kbytes 8 bytes EEA[2:0] 512 EEA[11:3] 8 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5V - 5.5V between VCC and GND, and wait at least 100µs. 2. Set RESET to “0” and toggle XTAL1 at least SIX times. 3.
ATmega128 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized in pages, see Table 123 on page 291. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”.
ATmega128 1. Set BS1 = “0” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high. (See Figure 137 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
ATmega128 Figure 137. Programming the Flash Waveforms F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B C ADDR. LOW DATA LOW D E DATA HIGH XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 124 on page 291. When programming the EEPROM, the program data is latched into a page buffer.
ATmega128 Figure 138. Programming the EEPROM Waveforms K A DATA 0x11 G B ADDR. HIGH ADDR. LOW C E B C DATA XX ADDR. LOW DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 293 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte ($00 - $FF). 3. B: Load Address Low Byte ($00 - $FF). 4.
ATmega128 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 293 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte.
ATmega128 4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). 5. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). 6. Set OE to “1”. Figure 140.
ATmega128 Figure 142. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: The timing requirements shown in Figure 141 (i.e. tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 143.
ATmega128 Table 126.
ATmega128 Figure 144. SPI Serial Programming and Verify(1) +2.7 - 5.5V VCC +2.7 - 5.5V(2) PDI PE0 PDO PE1 SCK PB1 AVCC XTAL1 RESET GND Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 2.7 - 5.5V.
ATmega128 3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all FOUR bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time.
ATmega128 Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location, VCC = 5V ±10% Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 5ms tWD_EEPROM 10ms tWD_ERASE 10ms Figure 145. .
ATmega128 Table 129. SPI Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
ATmega128 SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 323. Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is default shipped with the Fuse programmed.
ATmega128 Figure 146. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR AVR_RESET ($C) 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega128 PROG_COMMANDS ($5) PROG_PAGELOAD ($6) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: • Capture-DR: the result of the previous command is loaded into the data register. • Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega128 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega128 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 130. The state sequence when shifting in the programming commands is illustrated in Figure 149. Figure 148.
ATmega128 Table 130. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low Byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 1a. Chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega128 Table 130. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, H = 0 - Low Byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b.
ATmega128 Table 130. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, H = 0 - Low Byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a.
ATmega128 Figure 149. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR Virtual Flash Page Load Register 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page.
ATmega128 Figure 150. Virtual Flash Page Load Register STROBES TDI State machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
ATmega128 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming Enable Register. 4.
ATmega128 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3.
ATmega128 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Extended Fuse byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table Note: on page 299). 6. Load data byte using programming instructions 6e.
ATmega128 Electrical Characteristics Note: Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature .....................................
ATmega128 TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Active 4MHz, VCC = 3V (ATmega128L) 5 5.5 Active 8MHz, VCC = 5V (ATmega128) 17 19 Idle 4MHz, VCC = 3V (ATmega128L) 2 2.
ATmega128 Speed Grades Figure 152. Maximum frequency vs. VCC 16MHz 8MHz Safe Operating Area 2.7V External Clock Drive Waveforms 4.5V 5.5V Figure 153. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 131. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.
ATmega128 Table 132. External RC Oscillator, Typical Frequencies Notes: R [kΩ](1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz 1. R should be in the range 3kΩ - 100kΩ, and C should be at least 20pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout.
ATmega128 Two-wire Serial Interface Characteristics Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 154. Table 133. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Min Max Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.
ATmega128 5. This requirement applies to all Atmel® AVR® ATmega128 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. Figure 154. Two-wire Serial Bus Timing tHIGH tof tr tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF SPI Timing Characteristics See Figure 155 and Figure 156 for details. Table 134.
ATmega128 Figure 155. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 156. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) MSB ...
ATmega128 ADC Characteristics Table 135. ADC Characteristics, Single Ended Channels Symbol Parameter Condition Resolution Single Ended Conversion Typ(1) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.5 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz 3.25 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Noise Reduction mode 1.5 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz Noise Reduction mode 3.
ATmega128 Table 136.
ATmega128 Table 136. ADC Characteristics, Differential Channels (Continued) Symbol Parameter VINT Internal Voltage Reference RREF Reference Input Resistance RAIN Analog Input Resistance Notes: Condition Min(1) Typ(1) Max(1) Units 2.3 2.56 2.7 V 55 32 kΩ 100 MΩ 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V.
ATmega128 External Data Memory Timing Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state 8MHz Oscillator Min Variable Oscillator Symbol Parameter Max Min Max 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 2 tAVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 57.5 0.
ATmega128 Table 139. External Data Memory Characteristics, 4.5 - 5.5V, SRWn1 = 1, SRWn0 = 0 4MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 15 tDVWH Data Valid to WR High 375 3.0tCLCL 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 325 3.0tCLCL-50 ns Table 140. External Data Memory Characteristics, 4.5 - 5.
ATmega128 Table 141. External Data Memory Characteristics, 2.7 - 5.5V, No Wait-state (Continued) 4MHz Oscillator Variable Oscillator Symbol Parameter Min Max Min 12 tRLRH RD Pulse Width 235 1.0tCLCL-15 13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20(1) 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 15 tDVWH Data Valid to WR High 250 1.0tCLCL Max Unit ns 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 Notes: 1. This assumes 50% clock duty cycle.
ATmega128 Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Data 5 Read Address 11 10 8 12 RD Figure 158. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev.
ATmega128 Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 160. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev.
ATmega128 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega128 Figure 162. Active Supply Current vs. Frequency (1 - 20MHz) 45 40 5.0V 35 4.5V ICC (mA) 30 25 20 4.0V 15 3.3V 3.0V 2.7V 10 5 3.6V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 163. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 4 25 °C -40 °C 85 °C ICC (mA) 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 164. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 8 -40 °C 25 °C 85 °C 7 6 ICC (mA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 165. Active Supply Current vs. VCC (Internal RC, Oscillator, 4MHz) 14 -40 °C 25 °C 85 °C 12 ICC (mA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 166. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 25 -40 °C 25 °C 85 °C 20 ICC (mA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 167. Active Supply Current vs. VCC (32kHz External Oscillator) 140 120 25 °C ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Idle Supply Current Figure 168. Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 1.4 1.2 5.5V ICC (mA) 1 5.0V 4.5V 0.8 4.0V 3.6V 3.3V 3.0V 2.7V 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 169. Idle Supply Current vs. Frequency (1 - 20MHz) 25 5.5V 20 5.0V 4.5V 15 ICC (mA) 4.0V 10 3.6V 3.3V 5 3.0V 2.
ATmega128 Figure 170. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 85 °C 25 °C -40 °C 1.4 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 171. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 3 85 °C 25 °C -40 °C 2.5 ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 172. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 6 -40 °C 25 °C 85 °C 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 173. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 12 -40 °C 25 °C 85 °C 10 ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 174. Idle Supply Current vs. VCC (32kHz External Oscillator) 60 50 25 °C ICC (uA) 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 175. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4.5 4 85 °C 3.5 ICC (uA) 3 2.5 2 1.5 -40 °C 25 °C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 176. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 35 30 85 °C 25 °C -40 °C ICC (uA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 177. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 16 25 °C 14 12 ICC (uA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Standby Supply Current Figure 178. Standby Supply Current vs. VCC, 0.2 6 MHz Xtal 0.18 6 MHz Res 0.16 0.14 4 MHz Res 4 MHz Xtal ICC (mA) 0.12 0.1 2 MHz Res 2 MHz Xtal 0.08 455 kHz Res 1 MHz Res 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 179. Standby Supply Current vs. VCC (CKOPT programmed) 2.5 16 MHz Xtal 2 12 MHz Xtal 1.5 ICC (mA) 6 MHz Xtal 4 MHz Xtal 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Pin Pull-up Figure 180. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 85 °C 25 °C 120 -40 °C IOP (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 181. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 85 °C 25 °C 70 60 -40 °C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega128 Pin Driver Strength Figure 182. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 90 80 -40 °C 70 25 °C IOH (mA) 60 85 °C 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 VOH (V) Figure 183. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 30 -40 °C 25 25 °C 85 °C IOH (mA) 20 15 10 5 0 0.5 1 1.5 2 2.
ATmega128 Figure 184. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 90 -40 °C 80 25 °C 70 IOL (mA) 60 85 °C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 185. I/O Pin Sink Current vs. Output Voltage, VCC = 2.7V 35 -40 °C 30 25 °C 25 IOL (mA) 85 °C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega128 Pin Thresholds and Hysteresis Figure 186. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) 2.2 -40 °C 25 °C 85 °C 2 Threshold (V) 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 187. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘0’) 1.6 -40 °C 25 °C 85 °C 1.5 Threshold (V) 1.4 1.3 1.2 1.1 1 0.9 0.8 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 188. I/O Pin Input Hysteresis vs. VCC 0.7 85 °C 25 °C -40 °C 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 189. BOD Threshold vs. Temperature (BODLEVEL is 4.0V) 4.4 4.2 Threshold (V) Rising VCC 4 Falling VCC 3.8 3.6 3.
ATmega128 Figure 190. BOD Threshold vs. Temperature (BODLEVEL is 2.7V) 3 2.8 Threshold (V) Rising VCC 2.6 Falling VCC 2.4 2.2 2 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 191. Bandgap Voltage vs. Operating Voltage 1.275 85 °C 1.27 Bandgap Voltage (V) -40 °C 1.265 25 °C 1.26 1.255 1.25 2.5 3 3.5 4 4.5 5 5.
ATmega128 Internal Oscillator Speed Figure 192. Watchdog Oscillator Frequency vs. VCC 1220 -40 °C 25 °C 1200 85 °C 1180 FRC (kHz) 1160 1140 1120 1100 1080 1060 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 193. Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.02 5.5V 1 5.0V 4.5V 4.0V 3.6V 3.3V FRC (MHz) 0.98 0.96 0.94 2.7V 0.92 0.
ATmega128 Figure 194. Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.02 -40 °C 25 °C 85 °C 1 FRC (MHz) 0.98 0.96 0.94 0.92 0.9 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 195. 1MHz RC Oscillator Frequency vs. Osccal Value 1.5 25 °C 1.4 1.3 1.2 FRC (MHz) 1.1 1 0.9 0.8 0.7 0.6 0.5 0.
ATmega128 Figure 196. Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2.05 5.5V 2 5.0V FRC (MHz) 1.95 4.5V 4.0V 1.9 3.6V 3.3V 1.85 2.7V 1.8 1.75 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 197. Calibrated 2MHz RC Oscillator Frequency vs. VCC 2.05 -40 °C 25 °C FRC (MHz) 2 85 °C 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 198. 2MHz RC Oscillator Frequency vs. Osccal Value 4 25 °C 3.5 FRC (MHz) 3 2.5 2 1.5 1 0.5 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 199. Calibrated 4MHz RC Oscillator Frequency vs. Temperature 4.1 4.05 4 5.5V 5.0V 4.5V FRC (MHz) 3.95 3.9 3.85 4.0V 3.8 3.6V 3.3V 3.75 3.7 2.7V 3.65 3.
ATmega128 Figure 200. Calibrated 4MHz RC Oscillator Frequency vs. VCC 4.1 -40 °C 4.05 25 °C 4 85 °C FRC (MHz) 3.95 3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 201. 4MHz RC Oscillator Frequency vs.
ATmega128 Figure 202. Calibrated 8MHz RC OscillatorOFrequency C 8 C OSC QU Cvs. TemperatureU 8.4 8.2 8 5.5V FRC (MHz) 7.8 5.0V 7.6 4.5V 7.4 4.0V 7.2 3.6V 7 3.3V 6.8 2.7V 6.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 203. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.4 8.2 -40 °C 8 25 °C 85 °C FRC (MHz) 7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 204. 8MHz RC Oscillator Frequency vs. Osccal Value 16 25 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Current Consumption of Peripheral Units Figure 205. Brownout Detector Current vs. VCC 25 20 -40 °C 25 °C 85 °C ICC (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 206. ADC Current vs. AVCC (ADC at 50kHz) 600 -40 °C 25 °C 85 °C 500 ICC (uA) 400 300 200 100 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 207. ADC Current vs. AVCC (ADC at 1MHz) 250 25 °C 85 °C -40 °C 200 ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 208. Analog Comparator Current vs. VCC 100 85 °C 90 25 °C -40 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 209. Programming Current vs. VCC 9 -40 °C 8 7 25 °C ICC (mA) 6 85 °C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Current Consumption in Reset and Reset Pulse width Figure 210. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 4.5 4 5.5V 3.5 5.0V 4.5V 4.0V 3.6V 3.3V 3.0V 2.7V ICC (mA) 3 2.5 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 211. Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) , 40 5.5V 35 5.0V 30 4.5V ICC (mA) 25 4.0V 20 3.6V 3.3V 3.0V 2.
ATmega128 Figure 212. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5.0V) 120 25 °C -40 °C 100 85 °C IRESET (uA) 80 60 40 20 0 0 1 2 3 4 5 6 VRESET (V) Figure 213. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V 60 25 °C -40 °C 50 85 °C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega128 Figure 214. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as ‘1’) 2.5 2 Threshold (V) -40 °C 1.5 25 °C 85 °C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 215. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as ‘0’) 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Figure 216. Reset Input Pin Hysteresis vs. VCC 0.5 0.45 Input Hysteresis (mV) 0.4 -40 °C 0.35 0.3 0.25 0.2 25 °C 0.15 0.1 85 °C 0.05 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 217. Reset Pulse width vs. VCC (External Clock, 1MHz) 1.2 Pulsewidth (µs) 1 0.8 0.6 85 °C 25 °C -40 °C 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
ATmega128 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ($FF) Reserved – – – – – – – – ..
ATmega128 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ($61) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 88 ($60) Reserved – – – – – – – – $3F ($5F) SREG I T H S V N Z C 10 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 13 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 36 $3B ($5B) RAMPZ – – – – – – – RA
ATmega128 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 87 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 88 Notes: Page 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them.
ATmega128 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Reg
ATmega128 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None #Clocks 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd,
ATmega128 Instruction Set Summary (Continued) Mnemonics Description Operation Flags SEV Operands Set Twos Complement Overflow. V←1 V #Clocks 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 1 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr.
ATmega128 Ordering Information Speed (MHz) 8 16 8 16 Notes: Ordering Code(1) Package(2) 2.7 – 5.5V ATmega128L-8AU ATmega128L-8AUR(3) ATmega128L-8MU ATmega128L-8MUR(3) 64A 64A 64M1 64M1 4.5 – 5.5V ATmega128-16AU ATmega128-16AUR(3) ATmega128-16MU ATmega128-16MUR(3) 64A 64A 64M1 64M1 3.0 – 5.5V ATmega128L–8AN ATmega128L–8ANR(3) ATmega128L–8MN ATmega128L–8MNR(3) 64A 64A 64M1 64M1 4.5 – 5.
ATmega128 Packaging Information 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
ATmega128 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b e BOTTOM VIEW Notes: Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.45 K 1.
ATmega128 Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. F to M • • • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1.
ATmega128 SEI ; set global interrupt enable 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly.
ATmega128 Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Rev. 2467X-06/11 1. Corrected typos in “Ordering Information” on page 368. Rev. 2467W-05/11 1. Added Atmel QTouch Library Support and QTouch Sensing Capability Features. 2. Updated “DC Characteristics” on page 318. RRST maximum value changed from 60kΩ to 85kΩ. 3.
ATmega128 Rev. 2467Q-05/08 1. Updated “Preventing EEPROM Corruption” on page 24. Removed sentence “If the detection level of the internal BOD does not match the needed detection level, and external low VCC Reset Protection circuit can be used.“ 2. Updated Table 85 on page 196 in “Examples of Baud Rate Setting” on page 193. Remomved examples of frequencies above 16MHz. 3. Updated Figure 114 on page 238. Inductor value corrected from 10mH to 10µH. 4. Updated description of “Version” on page 253. 5.
ATmega128 Rev. 2467N-03/06 1. Updated note for Figure 1 on page 2. 2. Updated “Alternate Functions of Port D” on page 77. 3. Updated “Alternate Functions of Port G” on page 84. 4. Updated “Phase Correct PWM Mode” on page 100. 5. Updated Table 59 on page 133, Table 60 on page 133. 6. Updated “Bit 2 – TOV3: Timer/Counter3, Overflow Flag” on page 141. 7. Updated “Serial Peripheral Interface – SPI” on page 162. 8. Updated Features in “Analog to Digital Converter” on page 230 9.
ATmega128 Rev. 2467J-12/03 1. Updated “Calibrated Internal RC Oscillator” on page 41. Rev. 2467I-09/03 1. Updated note in “XTAL Divide Control Register – XDIV” on page 36. 2. Updated “JTAG Interface and On-chip Debug System” on page 48. 3. Updated values for VBOT (BODLEVEL = 1) in Table 19 on page 50. 4. Updated “Test Access Port – TAP” on page 246 regarding JTAGEN. 5. Updated description for the JTD bit on page 255. 6. Added a note regarding JTAGEN fuse to Table 118 on page 288. 7.
ATmega128 2. Added the section “Using all Locations of External Memory Smaller than 64 Kbyte” on page 32. 3. Added the section “Default Clock Source” on page 37. 4. Renamed SPMCR to SPMCSR in entire document. 5. When using external clock there are some limitations regards to change of frequency. This is descried in “External Clock” on page 42 and Table 131, “External Clock Drive,” on page 320. 6.
ATmega128 6. Improved description on how to do a polarity check of the ADC differential results in “ADC Conversion Result” on page 241. 7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 256. 8. Improved description of addressing during SPM (usage of RAMPZ) on “Addressing the Flash During Self-Programming” on page 278, “Performing Page Erase by SPM” on page 280, and “Performing a Page Write” on page 280. 9. Added not regarding OCDEN Fuse below Table 118 on page 288. 10.
ATmega128 See “Programming the Fuses” on page 317 and “Reading the Fuses and Lock Bits” on page 317.
ATmega128 Table of Contents Features 1 Pin Configurations 2 Overview 2 Block Diagram 3 ATmega103 and ATmega128 Compatibility 4 Pin Descriptions 5 Resources 8 Data Retention 8 About Code Examples 9 AVR CPU Core 10 Introduction 10 Architectural Overview 10 ALU – Arithmetic Logic Unit 11 Status Register 11 General Purpose Register File 12 Stack Pointer 14 Instruction Execution Timing 14 Reset and Interrupt Handling 15 AVR ATmega128 Memories 18 In-System Reprogrammable Flash Program Memory 18 SRAM Data Memor
ATmega128 Power-down Mode 46 Power-save Mode 46 Standby Mode 47 Extended Standby Mode 47 Minimizing Power Consumption 48 System Control and Reset 50 Internal Voltage Reference 54 Watchdog Timer 55 Timed Sequences for Changing the Configuration of the Watchdog Timer 58 Interrupts 60 Interrupt Vectors in ATmega128 60 I/O Ports 66 Introduction 66 Ports as General Digital I/O 67 Alternate Port Functions 71 Register Description for I/O Ports 87 External Interrupts 90 8-bit Timer/Counter0 with PWM and Asynchr
ATmega128 Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers 143 8-bit Timer/Counter2 with PWM 145 Overview 145 Timer/Counter Clock Sources 146 Counter Unit 146 Output Compare Unit 147 Compare Match Output Unit 148 Modes of Operation 149 Timer/Counter Timing Diagrams 155 8-bit Timer/Counter Register Description 157 Output Compare Modulator (OCM1C2) 161 Overview 161 Description 161 Serial Peripheral Interface – SPI 163 SS Pin Functionality 167 Data Modes 170 USART 171 Overview 171 Clock Generat
ATmega128 Analog to Digital Converter 230 Features 230 Operation 232 Starting a Conversion 232 Prescaling and Conversion Timing 233 Changing Channel or Reference Selection 235 ADC Noise Canceler 236 ADC Conversion Result 241 JTAG Interface and On-chip Debug System 246 Features 246 Overview 246 Test Access Port – TAP 246 TAP Controller 248 Using the Boundary-scan Chain 249 Using the On-chip Debug System 249 On-chip Debug Specific JTAG Instructions 250 On-chip Debug Related Register in I/O Memory 251 Using t
ATmega128 Serial Downloading 300 SPI Serial Programming Pin Mapping 300 Programming Via the JTAG Interface 305 Electrical Characteristics 318 Absolute Maximum Ratings* 318 DC Characteristics 318 Speed Grades 320 External Clock Drive Waveforms 320 External Clock Drive 320 Two-wire Serial Interface Characteristics 322 SPI Timing Characteristics 323 ADC Characteristics 325 External Data Memory Timing 328 Typical Characteristics 333 Register Summary 362 Instruction Set Summary 365 Ordering Information 368 368
ATmega128 Rev.
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