Datasheet

56
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
There are three alternative ways to disable the OCD system:
• Disable the OCDEN Fuse
• Disable the JTAGEN Fuse
• Write one to the JTD bit in MCUCR
11.10 Register Description
11.10.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 11-2.
Note: 1. Standby modes are only recommended for use with external crystals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
11.10.2 PRR0 – Power Reduction Register 0
• Bit 7 - PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
Bit 76543210
0x33 (0x53) ––––SM2SM1SM0SESMCR
Read/Write RRRRR/W R/W R/W R/W
Initial Value00000000
Table 11-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
1 1 0 Standby
(1)
1 1 1 Extended Standby
(1)
Bit 7 6 543 2 1 0
(0x64) PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR0
Read/Write R/W R/W R/W RR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0