Datasheet

49
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” for
details.
10.10 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
10.11 Timer/Counter Oscillator
The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter-
nal clock source. See Figure 10-2 on page 43 for crystal connection.
Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to
logic one. See “Asynchronous Operation of Timer/Counter2” on page 184 for further description
on selecting external clock as input instead of a 32kHz crystal.
10.12 System Clock Prescaler
The ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system clock can
be divided by setting the “CLKPR – Clock Prescale Register” on page 50. This feature can be
used to decrease the system clock frequency and the power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in Table 10-15 on page 51.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to
zero.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.