Datasheet

v
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
24 2-wire Serial Interface .......................................................................... 241
24.1 Features ........................................................................................................241
24.2 2-wire Serial Interface Bus Definition ............................................................241
24.3 Data Transfer and Frame Format ..................................................................242
24.4 Multi-master Bus Systems, Arbitration and Synchronization .........................245
24.5 Overview of the TWI Module .........................................................................246
24.6 Using the TWI ................................................................................................249
24.7 Transmission Modes .....................................................................................252
24.8 Multi-master Systems and Arbitration ............................................................265
24.9 Register Description ......................................................................................266
25 AC – Analog Comparator .................................................................... 271
25.1 Analog Comparator Multiplexed Input ...........................................................271
25.2 Register Description ......................................................................................272
26 ADC – Analog to Digital Converter ..................................................... 275
26.1 Features ........................................................................................................275
26.2 Operation .......................................................................................................276
26.3 Starting a Conversion ....................................................................................277
26.4 Prescaling and Conversion Timing ................................................................278
26.5 Changing Channel or Reference Selection ...................................................282
26.6 ADC Noise Canceler .....................................................................................283
26.7 ADC Conversion Result .................................................................................288
26.8 Register Description ......................................................................................289
27 JTAG Interface and On-chip Debug System ..................................... 296
27.1 Features ........................................................................................................296
27.2 Overview ........................................................................................................296
27.3 TAP - Test Access Port .................................................................................297
27.4 Using the Boundary-scan Chain ....................................................................299
27.5 Using the On-chip Debug System .................................................................299
27.6 On-chip Debug Specific JTAG Instructions ...................................................300
27.7 Using the JTAG Programming Capabilities ...................................................301
27.8 Bibliography ...................................................................................................301
27.9 On-chip Debug Related Register in I/O Memory ...........................................301
28 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 302
28.1 Features ........................................................................................................302
28.2 System Overview ...........................................................................................302