Datasheet

38
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 9-1 on page 28. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire
external memory address space is treated as one sector. When the entire SRAM address space
is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.
• Bit 3:2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see Table 9-3.
• Bit 1:0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see Table 9-3.
Note: 1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figures
9-3 through Figures 9-6 for how the setting of the SRW bits affects the timing.
9.4.2 XMCRB – External Memory Control Register B
Table 9-2. Sector limits with different settings of SRL2:0
SRL2 SRL1 SRL0 Sector Limits
00x
Lower sector = N/A
Upper sector = 0x2200 - 0xFFFF
010
Lower sector = 0x2200 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
011
Lower sector = 0x2200 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
100
Lower sector = 0x2200 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
101
Lower sector = 0x2200 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
110
Lower sector = 0x2200 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
111
Lower sector = 0x2200 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
Table 9-3. Wait States
(1)
SRWn1 SRWn0 Wait States
00 No wait-states
01 Wait one cycle during read/write strobe
10 Wait two cycles during read/write strobe
11
Wait two cycles during read/write and wait one cycle before driving out new
address
Bit 765 4 3 210
(0x75) XMBK – – – – XMM2 XMM1 XMM0 XMCRB
Read/Write R/W RR R RR/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0