Datasheet

376
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 31-7. SPI Interface Timing Requirements (Master Mode)
Figure 31-8. SPI Interface Timing Requirements (Slave Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSBLSB
LSBMSB
...
...
61
22
345
8
7
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSBLSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16