Datasheet

350
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
30.8.1 Serial Programming Pin Mapping
Figure 30-10. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V.When
programming the EEPROM, an auto-erase cycle is built into the self-timed programming oper-
ation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
30.8.2 Serial Programming Algorithm
When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising
edge of SCK.
When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling
edge of SCK. See Figure 30-12 on page 353 for timing details.
Table 30-15. Pin Mapping Serial Programming
Symbol
Pins
(TQFP-100)
Pins
(TQFP-64) I/O Description
PDI PB2 PE0 I Serial Data in
PDO PB3 PE1 O Serial Data out
SCK PB1 PB1 I Serial Clock
VCC
GND
XT AL1
SCK
PDO
PDI
RESET
+1.8V - 5.5V
AVCC
+1.8V - 5.5V
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