Datasheet
332
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page
318 and “RWW – Read-While-Write Section” on page 318.
Notes: 1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See “Addressing the Flash During Self-Programming” on page 322 for details about the use of
Z-pointer during Self-Programming.
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.
29.7 Register Description
29.7.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
Table 29-14. Read-While-Write Limit, ATmega2560/2561
Section
(1)
Pages Address
Read-While-Write section (RWW) 992 0x00000 - 0x1EFFF
No Read-While-Write section (NRWW) 32 0x1F000 - 0x1FFFF
Table 29-15. Explanation of different variables used in Figure 29-3 on page 322 and the map-
ping to the Z-pointer, ATmega2560/2561
Variable
Corresponding
Z-value
(2)
Description
(1)
PCMSB 16
Most significant bit in the Program Counter. (The
Program Counter is 17 bits PC[16:0]).
PAG EM SB 6
Most significant bit which is used to address the
words within one page (128 words in a page
requires seven bits PC [6:0]).
ZPCMSB Z17:Z16
(3)
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
ZPAGEMSB Z7
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB +
1.
PCPAGE PC[16:7] Z17
(3)
:Z8
Program Counter page address: Page select, for
Page Erase and Page Write.
PCWORD PC[6:0] Z7:Z1
Program Counter word address: Word select, for
filling temporary buffer (must be zero during Page
Write operation).
Bit 7 6 5 4 3 2 1 0
0x37 (0x57)
SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/Write R/W RR/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0