Datasheet
32
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 9-5. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0
(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal
or external).
Figure 9-6. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1
(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
9.1.5 Using all Locations of External Memory Smaller than 64Kbytes
Since the external memory is mapped after the internal memory as shown in Figure 9-1 on page
28, the external memory is not addressed when addressing the first 8,704 bytes of data space. It
may appear that the first 8,704 bytes of the external memory are inaccessible (external memory
addresses 0x0000 to 0x21FF). However, when connecting an external memory smaller than
64Kbytes, for example 32Kbytes, these locations are easily accessed simply by addressing from
address 0x8000 to 0xA1FF. Since the External Memory Address bit A15 is not connected to the
external memory, addresses 0x8000 to 0xA1FF will appear as addresses 0x0000 to 0x21FF for
the external memory. Addressing above address 0xA1FF is not recommended, since this will
address an external memory location that is already accessed by another (lower) address. To
ALE
T1 T2 T3
Write
Read
WR
T6
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4 T5
ALE
T1 T2 T3
Write
Read
WR
T7
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4 T5 T6