Datasheet

275
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
26. ADC – Analog to Digital Converter
26.1 Features
• 10-bit Resolution
• 1 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 13µs - 260µs Conversion Time
• Up to 76.9kSPS (Up to 15kSPS at Maximum Resolution)
• 16 Multiplexed Single Ended Input Channels
• 14 Differential input channels
• 4 Differential Input Channels with Optional Gain of 10× and 200×
• Optional Left Adjustment for ADC Result Readout
• 0V - V
CC
ADC Input Voltage Range
• 2.7V - V
CC
Differential ADC Voltage Range
• Selectable 2.56V or 1.1V ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The ATmega640/1280/1281/2560/2561 features a 10-bit successive approximation ADC. The
ADC is connected to an 8/16-channel Analog Multiplexer which allows eight/sixteen single-
ended voltage inputs constructed from the pins of Port F and Port K. The single-ended voltage
inputs refer to 0V (GND).
The device also supports 16/32 differential voltage input combinations. Four of the differential
inputs (ADC1 & ADC0, ADC3 & ADC2, ADC9 & ADC8 and ADC11 & ADC10) are equipped with
a programmable gain stage, providing amplification steps of 0 dB (1×), 20 dB (10×) or 46 dB
(200×) on the differential input voltage before the ADC conversion. The 16 channels are split in
two sections of 8 channels where in each section seven differential analog input channels share
a common negative terminal (ADC1/ADC9), while any other ADC input in that section can be
selected as the positive input terminal. If 1× or 10× gain is used, 8 bit resolution can be
expected. If 200× gain is used, 7 bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 26-1
on page 276.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than
±0.3V from V
CC
. See the paragraph “ADC Noise Canceler” on page 283 on how to connect this
pin.
Internal reference voltages of nominally 1.1V, 2.56V or AVCC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise
performance.
The Power Reduction ADC bit, PRADC, in “PRR0 – Power Reduction Register 0” on page 56
must be disabled by writing a logical zero to enable the ADC.