Datasheet

240
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to “SPI Data Modes and Timing” on page 233 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to “SPI Data Modes and Timing” on page 233 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to “SPI Data Modes and
Timing” on page 233 for details.
23.6.5 UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 227.
Table 23-4. Comparison of USART in MSPIM mode and SPI pins.
USART_MSPIM SPI Comment
TxDn MOSI Master Out only
RxDn MISO Master In only
XCKn SCK (Functionally identical)
(N/A) SS Not supported by USART in MSPIM