Datasheet

226
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 22-5. UPMn Bits Settings
UPMn1 UPMn0 Parity Mode
00 Disabled
01 Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 22-6. USBS Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 22-7. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
000 5-bit
001 6-bit
010 7-bit
011 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
111 9-bit
Table 22-8. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed (Output of
TxDn Pin)
Received Data Sampled (Input on RxDn
Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge