Datasheet

162
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
17.11.10 TCCR3C – Timer/Counter 3 Control Register C
17.11.11 TCCR4C – Timer/Counter 4 Control Register C
17.11.12 TCCR5C – Timer/Counter 5 Control Register C
•
Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
17.11.13 TCNT1H and TCNT1L – Timer/Counter 1
17.11.14 TCNT3H and TCNT3L – Timer/Counter 3
Bit 7654 3210
(0x92) FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/Write WWW R RRRR
Initial Value 0 0 0 0 0 0 0 0
Bit 7654 3210
(0xA2) FOC4A FOC4B FOC4C – – – – – TCCR4C
Read/Write WWW R RRRR
Initial Value 0 0 0 0 0 0 0 0
Bit 7654 3210
(0x122) FOC5A FOC5B FOC3C – – – – – TCCR5C
Read/Write WWW R RRRR
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x85) TCNT1[15:8] TCNT1H
(0x84) TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x95) TCNT3[15:8] TCNT3H
(0x94) TCNT3[7:0] TCNT3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0