Datasheet

159
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 17-2 on page 148. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. For more information on the different
modes, see “Modes of Operation” on page 148.
Table 17-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at BOTTOM. See “Fast PWM Mode” on page 150. for more details.
Table 17-3. Compare Output Mode, non-PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0 Description
00 Normal port operation, OCnA/OCnB/OCnC disconnected
0 1 Toggle OCnA/OCnB/OCnC on compare match
1 0 Clear OCnA/OCnB/OCnC on compare match (set output to low level)
1 1 Set OCnA/OCnB/OCnC on compare match (set output to high level)
Table 17-4. Compare Output Mode, Fast PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0 Description
00 Normal port operation, OCnA/OCnB/OCnC disconnected
01
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B/OC1C disconnected
10
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at
BOTTOM (non-inverting mode)
11
Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at
BOTTOM (inverting mode)