Datasheet
12
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
7. AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Fl ash
Pr o gr am
Memory
Instruction
Re g i s t e r
Instruction
Decoder
Pr o gr am
Co u n t e r
Control Lines
32 x 8
Gen er al
Pu r p ose
Re g i s t e r s
ALU
St a t u s
and Cont rol
I/O Lines
EEPRO M
Data Bus 8-bit
Data
SRA M
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Wat chdog
Ti mer
Analog
Comparat or
I/O Module 2
I/O Module1
I/O Module n