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Features

•

Industry Standard Architecture

– Emulates Many 20-Pin PALs

– Low Cost Easy-to-Use Software Tools

•

High-Speed Electrically Erasable Programmable Logic Devices

– 7.5 ns Maximum Pin-to-Pin Delay

•

Several Power Saving Options

•

CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pull-Up Resistors

•

Advanced Flash Technology

– Reprogrammable

– 100% Tested

•

High Reliability CMOS Process

– 20 Year Data Retention

– 100 Erase/Write Cycles

– 2,000V ESD Protection

– 200 mA Latchup Immunity

•

Commercial, and Industrial Temperature Ranges

•

Dual-in-Line and Surface Mount Packages in Standard Pinouts

Block Diagram

Device I

, Stand-By I

, Active

ATF16V8B 50 mA 55 mA

ATF16V8BQ 35 mA 40 mA

ATF16V8BQL 5 mA 20 mA

Rev. 0364E–07/98

High-

Performance

Flash PLD

ATF16V8B

Pin Configurations

Pin Name Function

CLK Clock

I Logic Inputs

I/O Bidirectional Buffers

Output Enable

+5 V Supply

TSSOP Top View

I/CLK

GND

VCC

I/O

I9/OE

DIP/SOIC PLCC Top View

Summary of content (18 pages)

PAGE 1
Features • Industry Standard Architecture – Emulates Many 20-Pin PALs® – Low Cost Easy-to-Use Software Tools • High-Speed Electrically Erasable Programmable Logic Devices – 7.
PAGE 2
Description The ATF16V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 7.5 ns are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges. Several low power options allow selection of the best solution for various types of power-limited applications.
PAGE 3
ATF16V8B DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(MAX) IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC Min Typ Max Units -35 -100 µA 10 µA Com. 55 85 mA Ind. 55 95 mA Com. 50 75 mA Ind. 50 80 mA Com. 35 55 mA Com. 5 10 mA Ind. 5 15 mA Com. 60 90 mA Ind. 60 100 mA Com. 55 85 mA Ind. 55 95 mA Com. 40 55 mA Com. 20 35 mA Ind.
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AC Waveforms(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified. AC Characteristics(1) -7(2) -10 -15 -25 Symbol Parameter tPD Input or Feedback to Non-Registered Output tCF Clock to Feedback tCO Clock to Output 2 tS Input or Feedback Setup Time 5 7.
PAGE 5
ATF16V8B Input Test Waveforms and Measurement Levels: Output Test Loads: Commercial tR, tF < 5 ns (10% to 90%) Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units CIN 5 8 pF VIN = 0 V COUT 6 8 pF VOUT = 0 V Note: Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF16V8Bs are designed to reset during power up.
PAGE 6
Electronic Signature Word Input and I/O Pull-Ups There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V CC . This ensures that all logic array inputs are at known states.
PAGE 7
ATF16V8B Macrocell Configuration Software compilers support the three different OMC modes as different device types. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode.
PAGE 8
Registered Mode Logic Diagram 8 ATF16V8B
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ATF16V8B ATF16V8B Complex Mode PAL Device Emulation/PAL Replacement In the Complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each mac- rocell has seven product terms going to the sum term and one product term enabling the output.
PAGE 10
Complex Mode Logic Diagram 10 ATF16V8B
PAGE 11
ATF16V8B Simple Mode Logic Diagram 11
PAGE 12
SUPPLY CURRENT vs. INPUT FREQUENCY SUPPLY CURRENT vs. INPUT FREQUENCY ATF16V8BL/BQL (VCC = 5V, TA = 25C) ATF16V8B/BQ (VCC = 5V, TA = 25C) 75 75 ATF16V8BL ATF16V8B I C C 50 m A 25 ATF16V8BQ 0 25 50 75 100 SUPPLY CURRENT vs. SUPPLY VOLTAGE ATF16V8B/BQ (TA = 25C) 65 ATF16V8B 55 ATF16V8BQ 45 35 25 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (TA = 25C) -10 -12 I O H -14 -16 -18 m A -20 -22 -24 4.5 4.7 4.9 5.1 5.
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ATF16V8B NORMALIZED TPD vs. SUPPLY VOLTAGE (TA=25°C) 1.3 N O R M T P D 1.15 ATF16V8B/BQ 1 ATF16V8BQL 0.85 0.7 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) NORMALIZED TCO vs. SUPPLY VOLTAGE(TA=25°C) 1.3 N O 1.15 ATF16V8B/BQ R M 1 ATF16V8BQL T C 0.85 O 0.7 4.50 4.75 5.00 5.25 5.
PAGE 14
ATF16V8B
PAGE 15
ATF16V8B Ordering Information tPD (ns) tS (ns) tCO (ns) Ordering Code (1) Package Operation Range 7.5 5 5 ATF16V8B-7JC ATF16V8B-7PC(1) ATF16V8B-7SC(1) ATF16V8B-7XC(1) 20J 20P3 20S 20X Commercial (0°C to 70°C) 10 7.
PAGE 16
Ordering Information tPD (ns) tS (ns) tCO (ns) 10 7.
PAGE 17
ATF16V8B Packaging Information 20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AA 20P3, 20-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AD 1.060(26.9) .980(24.9) PIN 1 .280(7.11) .240(6.10) .090(2.29) MAX .900(22.86) REF .210(5.33) MAX .005(.127) MIN SEATING PLANE .015(.381) MIN .150(3.81) .115(2.92) .022(.559) .014(.356) .070(1.78) .045(1.13) .110(2.79) .090(2.
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