User guide

Evaluation Kit Hardware
4-26 Evaluation Kit (EK) User Guide
11115A–ATARM–27-Jul-11
There is another 3.3V rail, VDDNF, supplied from the CM board. VDDNF is set to 3.3V in the current CM
design. The processors also support a 1.8V NAND Flash device, in which case VDDNF is set to 1.8V. In
order to avoid potential voltage conflict on user-defined applications, a level shifter is inserted between
the PIO lines on VDDNF rail and the 3.3V application.
Figure 4-19. Level Shifter For VDDNF Rail
4.3.3.3 JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a stan-
dard USB-to-JTAG in-circuit emulator such as SAM-ICE
™
.
Figure 4-20. JTAG Interface
3V3
C119 100nC118 100n
PD16
PD17
PD18
PD19
PD20
ZB_RSTN
ZB_SLPTR
EN5V_HDB#
EN5V_HDA#
EN5V_HDC#
MN18
SN74AVC8T245PWR
VCCA
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
B7
15
B6
16
B5
17
B4
18
B3
19
B2
20
B1
21
OE
22
VCCB2
23
VCCB1
24
GND1
11
GND2
12
GND3
13
B8
14
VDDNF
VDDIOP0
R46
100k
DNP
R47
100k
DNP
R48
100k
DNP
R49
100k
DNP
NRST
R58
0R
DNP
R51 0R
R50 0R
DNP
R54 0R
RTCK
TDI
TMS
TDO
NTRST
TCK
NRST
RTCK
NTRST
TCK
TMS
TDI
TDO
J9
BR20-H
12
34
56
78
910
1112
13
15
17
19
14
16
18
20
VDDIOP0
VDDIOP0