hub/switch user guide AT91

ARM RealView RVT Trace capture unit
is an add-on for RealView ICE to capture
output from the ARM Embedded Trace
Macrocell
™
. ARM RealView ICE supports
all ARM processors and can be expanded
with additional modules for extended
functionality, such as Trace capture.
Supported Platforms
Windows
®
2000, XP
Note: Cannot be used standalone.
This product is designed to be used in
conjunction with a RealView ICE run
control unit.
The ARM RealView ICE run control unit
provides the software and hardware interface
to ARM processor-based system-on-chip
(SoC) devices using the industry standard
JTAG connection. It is designed for optimum
performance with RealView Developer Suite
debugger, offering unparalleled depth and
breadth of support for ARM processor-
based devices and is currently only supported
by this debugger.
ARM RealView ICE supports all ARM
processors and can be expanded with
additional modules for extended functionality,
such as Trace capture. RealView ICE is an
essential tool in the ARM system debug
environment for devices that contain the
EmbeddedICE
®
logic and Embedded Trace
Macrocell™ components.
For more information please visit
www.arm.com/products/DevTools
CONTACTS
USA
Arrow Electronics
Phone: [phone]
e-mail: [e-mail]
EUROPE
Unique-memec
Phone: [phone]
e-mail:
[e-mail]
JAPAN/ASIA PACIFIC
YDC Corporation
Phone: [phone]
e-mail: [e-mail]
II-04
WEB SITE
www.arm.com
ARM
®
ARM REALVIEW
®
TRACE
™
CAPTURE UNIT
ARM REALVIEW
®
ICE &
MULTI-ICE JTAG INTERFACE UNIT
• Deep programmable depth trace buffer.
- 4 million processor cycles using a
4 bit trace port (with timestamp)
- 2 million processor cycles using a
8/16 bit trace port (with timestamp)
- 8 million processor cycles using
a 4 bit trace port (no timestamp)
- 4 million processor cycles using a
8/16 bit trace port (no timestamp)
• Maximum operating frequency
- Maximum trace clock frequency
250 MHz
• Fast on-the-fly trace data upload
• Fully variable trigger position
• ETM protocols v1.x, v2.x, v3.x for
ETM7
™
and ETM9
™
• ETM trace ports modes supported:
- Single and doubled edged clocking
- 4, 8, 16-bit data port widths
• Time stamp (48-bit) 10ns resolution
32 day duration
• High performance debug
• Code download up to 500
KBytes/sec at 10 MHz JTAG clock
• High speed single-stepping
• New differential signal probe for high
JTAG frequencies (up to 50MHz) and
longer cable lengths
• Low JTAG clock rates (down to
3kHz) support FPGA prototyping
(Lower clock rates planned)
• Network connection
• Ethernet 10/100baseT
• USB connection (Windows
platforms only) USB 1.1 & USB 2.0
C HAPTER II - JTAG ICE
I NTERFACES
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