Datasheet

78
AT8xC51SND1C
4109E–8051–06/03
Registers Table 84. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
Reset Value = 0000 1000b
Table 85. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
Reset Value = 1011 0010b
76543210
JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR
Bit
Number
Bit
Mnemonic Description
7 - 3 JUST4:0
Audio Stream Justification Bits
Refer to Section "Data Converter", page 74 for bits description.
2POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I
2
S mode).
1DSIZ
Audio Data Size
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
0HLR
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
76543210
SRC DRQEN MSREQ MUDRN - DUP1 DUP0 AUDEN
Bit
Number
Bit
Mnemonic Description
7SRC
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.
6 DRQEN
MP3 Decoded Data Request Enable Bit
Set to enable data request to the MP3 decoder and to start playing song.
Clear to disable data request to the MP3 decoder.
5MSREQ
Audio Sample Request Flag Mask Bit
Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
4 MUDRN
Audio Sample Under-run Flag Mask Bit
Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
3-
Reserved
The value read from this bit is always 0. Do not set this bit.
2 - 1 DUP1:0
Audio Duplication Factor
Refer to Table 83 for bits description.
0 AUDEN
Audio Interface Enable Bit
Set to enable the audio interface.
Clear to disable the audio interface.