Datasheet

21
AT8xC51SND1C
4109E–8051–06/03
Registers Table 21. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
Reset Value = XXXX 00X0b
Note: 1. ENBOOT bit is only available in AT89C51SND1C product.
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number
Bit
Mnemonic Description
7 - 6 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
5 ENBOOT
1
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h
to FFFFh.
Clear this bit to disable boot Flash.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3
General Flag
This bit is a general-purpose user flag.
20
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
1-Reserved for Data Pointer Extension.
0DPS
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.