Datasheet

194
AT8xC51SND1C
4109E–8051–06/03
Two-wire Interface
Timings Table 167. TWI Interface AC Timing
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·T
CLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. T
CLCL= T
OSC
= one oscillator clock period.
Waveforms Figure 150. Two Wire Waveforms
Symbol Parameter
INPUT
M in
Max
OUTPUT
M in
Max
T
HD; STA Start condition hold time 14·TCLCL
(4)
4.0 µs
(1)
TLOW SCL low time 16·TCLCL
(4)
4.7 µs
(1)
THIGH SCL high time 14·TCLCL
(4)
4.0 µs
(1)
TRC SCL rise time 1 µs-
(2)
TFC SCL fall time 0.3 µs0.3 µs
(3)
TSU; DAT1 Data set-up time 250 ns 20·TCLCL
(4)
- TRD
TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 µs
(1)
TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL
(4)
THD; DAT Data hold time 0 ns 8·TCLCL
(4)
- TFC
TSU; STA Repeated START set-up time 14·TCLCL
(4)
4.7 µs
(1)
TSU; STO STOP condition set-up time 14·TCLCL
(4)
4.0 µs
(1)
TBUF Bus free time 14·TCLCL
(4)
4.7 µs
(1)
TRD SDA rise time 1 µs -
(2)
TFD SDA fall time 0.3 µs0.3 µs
(3)
Tsu;DAT1
T
su
;STA
Tsu ;DAT2
T
hd
;STA
T
high
T
low
SDA
(INPUT/OUTPUT)
0.3 V
DD
0.7 V
DD
T
buf
T
su
;STO
0.7 V
DD
0.3 V
DD
T
rd
T
fd
T
rc
T
fc
SCL
(INPUT/OUTPUT)
T
hd;
DAT
T
su;
DAT3
START or Repeated START condition
START condition
STOP condition
Repeated START condition