Datasheet

191
AT8xC51SND1C
4109E–8051–06/03
Timings Test conditions: capacitive load on all pins= 50 pF.
Table 166. SPI Interface Master AC Timing
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
Note: 1. Value of this parameter depends on software.
Symbol Parameter Min Max Unit
Slave Mode
T
CHCH
Clock Period 2 T
PER
T
CHCX
Clock High Time 0.8 T
PER
T
CLCX
Clock Low Time 0.8 T
PER
T
SLCH
, T
SLCL
SS Low to Clock edge 100 ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 40 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 40 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 40 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
CLSH
, T
CHSH
SS High after Clock Edge 0 ns
T
SLOV
SS Low to Output Data Valid 50 ns
T
SHOX
Output Data Hold after SS High 50 ns
T
SHSL
SS High to SS Low
(1)
T
ILIH
Input Rise Time 2 µs
T
IHIL
Input Fall Time 2 µs
T
OLOH
Output Rise time 100 ns
T
OHOL
Output Fall Time 100 ns
Master Mode
T
CHCH
Clock Period 2 T
PER
T
CHCX
Clock High Time 0.8 T
PER
T
CLCX
Clock Low Time 0.8 T
PER
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 20 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 20 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 40 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
ILIH
Input Data Rise Time 2 µs
T
IHIL
Input Data Fall Time 2 µs
T
OLOH
Output Data Rise time 50 ns
T
OHOL
Output Data Fall Time 50 ns