Datasheet

187
AT8xC51SND1C
4109E–8051–06/03
Table 161. External 8-bit Bus Cycle - Data Write AC Timings
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
Waveforms Figure 142. External 8-bit Bus Cycle - Data Read Waveforms
Symbol Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
UnitMin Max Min Max
T
CLCL
Clock Period 50 50 ns
T
LHLL
ALE Pulse Width 2·T
CLCL
-15 T
CLCL
-15 ns
T
AVLL
Address Valid to ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLAX
Address hold after ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLWL
ALE Low to WR Low 3·T
CLCL
-30 1.5·T
CLCL
-30 ns
T
WLWH
WR Pulse Width 6·T
CLCL
-25 3·T
CLCL
-25 ns
T
WHLH
WR High to ALE High T
CLCL
-20 T
CLCL
+20 0.5·T
CLCL
-20 0.5·T
CLCL
+20 ns
T
AVWL
Address Valid to WR Low 4·T
CLCL
-30 2·T
CLCL
-30 ns
T
QVWH
Data Valid to WR High 7·T
CLCL
-20 3.5·T
CLCL
-20 ns
T
WHQX
Data Hold after WR High T
CLCL
-15 0.5·T
CLCL
-15 ns
T
AVDV
T
LLAX
T
RHDX
T
RHDZ
T
AVLL
T
AVRL
P2
P0
RD
ALE
T
LHLL
T
RLRH
Data In
A15:8
T
RLAZ
T
LLRL
T
RHLH
T
RLDV
D7:0A7:0