Datasheet

172
AT8xC51SND1C
4109E–8051–06/03
Registers Table 142. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
Reset Value = 0000 0000b
76543210
SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0
Bit
Number
Bit
Mnemonic Description
7 SSCR2
Synchronous Serial Control Rate Bit 2
Refer to Table 135 for rate description.
6SSPE
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
5SSSTA
Synchronous Serial Start Flag
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
4SSSTO
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
3SSI
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2SSAA
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if
SSGC set) is recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Master Transmitter Mode in progress
This bit has no specific effect when in master transmitter mode.
Slave Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Slave Transmitter Mode in progress
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
1 SSCR1
Synchronous Serial Control Rate Bit 1
Refer to Table 135 for rate description.
0 SSCR0
Synchronous Serial Control Rate Bit 0
Refer to Table 135 for rate description.