Datasheet

156
AT8xC51SND1C
4109E–8051–06/03
Registers Table 132. SPCON Register
SPCON (S:C3h) – SPI Control Register
Reset Value = 0001 0100b
Note: 1. When the SPI is disabled, SCK outputs high level.
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit
Number
Bit
Mnemonic Description
7SPR2
SPI Rate Bit 2
Refer to Table 131 for bit rate description.
6SPEN
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
5SSDIS
Slave Select Input Disable Bit
Set to disable SS
in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
Clear to enable SS
in both master and slave modes.
4MSTR
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
3CPOL
SPI Clock Polarity Bit
(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
2CPHA
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
1 - 0 SPR1:0
SPI Rate Bits 0 and 1
Refer to Table 131 for bit rate description.