Datasheet

143
AT8xC51SND1C
4109E–8051–06/03
Registers Table 125. SCON Register
SCON (S:98h) – Serial Control Register
Reset Value = 0000 0000b
76543210
FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
Bit
Mnemonic Description
7
FE
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
SM0
Serial Port Mode Bit 0
Refer to Table 123 for mode selection.
6SM1
Serial Port Mode Bit 1
Refer to Table 123 for mode selection.
5SM2
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address
recognition features.
Clear to disable the multiprocessor communication and automatic address
recognition features.
4REN
Receiver Enable Bit
Set to enable reception.
Clear to disable reception.
3TB8
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
2RB8
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit
received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
1TI
Transmit Interrupt Flag
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
0RI
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.