Features • MPEG I/II-Layer 3 Hardwired Decoder • • • • • • • • • • • • • • • • • • • • – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.
The AT83C51SND1C includes 64K Bytes of ROM memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
AT8xC51SND1C Pin Description Figure 2. AT89C51SND1C 80-pin QFP Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Pinouts 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AT89C51SND1C-RO (FLASH) AT83C51SND1C-RO (ROM) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.
Figure 3. AT8xC51SND1C 81-pin BGA Package 9 8 7 6 5 4 P4.6 P2.0/ A8 P4.0/ MISO P4.4 P4.7 P2.5/ A13 P4.2/ SCK VDD P0.2/ AD2 P0.3/ AD3 P5.0 ALE A P4.1/ MOSI P4.3/ SS P0.1/ AD1 P0.4/ AD4 P0.0/ AD0 ISP/ NC(1) P1.1 B P2.2/ A10 P2.1/ A9 P0.6 VSS P5.1 P1.0/ KIN0 P1.3/ KIN3 P1.2/ KIN2 C P2.4/ A12 P2.6/ A14 P4.5 P0.7/ AD7 P0.5/ AD5 P1.6/ SCL P1.7/ SDA P1.5 P1.4 D VDD P2.3/ A11 VSS P2.7/ A15 FILT PVDD X1 VDD E RST MCMD MCLK MDAT AVDD P3.
AT8xC51SND1C 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 4. AT8xC51SND1C 84-pin PLCC Package 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AT89C51SND1C-SR (FLASH) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.
Signals All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name Type Alternate Function Description P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. P1.
AT8xC51SND1C Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Alternate Function Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. P3.
Table 6. MutiMediaCard Interface Signal Description Signal Name Type Alternate Function MCLK O MMC Clock output Data or command clock transfer. - MCMD I/O MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. - MDAT I/O MMC Data line Bidirectional data channel.
AT8xC51SND1C Table 10. A/D Converter Signal Description Signal Name Type AIN1:0 I A/D Converter Analog Inputs - AREFP I Analog Positive Voltage Reference Input - AREFN I Analog Negative Voltage Reference Input This pin is internally connected to AVSS. - Description Alternate Function Table 11. Keypad Interface Signal Description Signal Name Type KIN3:0 I Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt.
Table 13. System Signal Description Signal Name Type Alternate Function Description RST I Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD.
AT8xC51SND1C Internal Pin Structure Table 15. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P1(2) P2(3) P3 P4 P53:0 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output N P0 MCMD MDAT ISP VSS ALE SCLK DCLK VDD P Output N DOUT DSEL MCLK VSS D+ Input/Output D+ D- D- Notes: 1.
Clock Controller The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an onchip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. Oscillator The AT8xC51SND1C X1 and X2 pins are the input and the output of a single-stage onchip inverter (see Figure 5) that can be configured with off-chip components such as a Pierce oscillator (see Figure 6).
AT8xC51SND1C Figure 7. Mode Switching Waveforms X1 X1 ÷ 2 X2 Bit Clock STD Mode Note: STD Mode X2 Mode(1) 1. In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (timers, etc.) will have their time reference divided by 2. For example, a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
Figure 9. PLL Filter Connection FILT R C2 C1 VSS PLL Programming VSS The PLL is programmed using the flow shown in Figure 10. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface clock frequencies. Figure 10.
AT8xC51SND1C Registers Table 16. CKCON Register CKCON (S:8Fh) – Clock Control Register 7 6 5 4 3 2 1 0 - WDX2 - - - T1X2 T0X2 X2 Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog Clock Control Bit Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Table 18. PLLNDIV Register PLLNDIV (S:EEh) – PLL N Divider Register 7 6 5 4 3 2 1 0 - N6 N5 N4 N3 N2 N1 N0 Bit Number Bit Mnemonic Description 7 - 6-0 N6:0 Reserved The value read from this bit is always 0. Do not set this bit. PLL N Divider 7 - bit N divider. Reset Value = 0000 0000b Table 19.
AT8xC51SND1C Program/Code Memory The AT8xC51SND1C implement 64K Bytes of on-chip program/code memory. Figure 11 shows the split of internal and external program/code memory spaces depending on the product. The AT83C51SND1C product provides the internal program/code memory in ROM memory while the AT89C51SND1C product provides it in Flash memory. These 2 products do not allow external code memory execution.
User Space This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the user’s application code. Flash Memory Architecture As shown in Figure 13 the AT89C51SND1C Flash memory is composed of four spaces detailed in the following paragraphs. Figure 13.
AT8xC51SND1C Hardware Security System The AT89C51SND1C implements three lock bits LB2:0 in the LSN of HSB (see Table 22) providing three levels of security for user’s program as described in Table 22 while the AT83C51SND1C is always set in read disabled mode. Level 0 is the level of an erased part and does not enable any security feature. Level 1 locks the hardware programming of both user and boot memories.
Figure 14. Hardware Boot Process Algorithm RESET Hard Cond? Software Process Hardware Process ISP = L? Prog Cond? BLJB = P? Standard Init ENBOOT = 0 PC = 0000h FCON = F0h Prog Cond Init ENBOOT = 1 PC = F000h FCON = F0h User’s Application Atmel’s Boot Loader Hard Cond Init ENBOOT = 1 PC = F000h FCON = 00h The software process (boot loader) is detailed in the “Boot Loader Datasheet” Document. Preventing Flash Corruption 20 See Section “Reset Recommendation to Prevent Flash Corruption”, page 47.
AT8xC51SND1C Registers Table 21. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Number 7-6 Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. - 1 Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash.
Hardware Bytes Table 22. HSB Byte – Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description X2B(1) 7 (2) 6 BLJB 5-4 - 3 - 2-0 LB2:0 X2 Bit Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode. Boot Loader Jump Bit Program this bit to execute the boot loader at address F000h on next reset. Unprogram (erase) this bit to execute user’s application at address 0000h on next reset.
AT8xC51SND1C Data Memory The AT8xC51SND1C provides data memory access in 2 different spaces: 1. The internal space mapped in three separate segments: – The lower 128 Bytes RAM segment – The upper 128 Bytes RAM segment – The expanded 2048 Bytes RAM segment 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 16. Lower 128 Bytes Internal RAM Organization 7Fh 30h 2Fh 20h 18h 10h 08h 00h Bit-Addressable Space (Bit Addresses 0-7Fh) 1Fh 17h 0Fh 4 Banks of 8 Registers R0-R7 07h Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. Expanded RAM The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh using indirect addressing mode through MOVX instructions.
AT8xC51SND1C External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 17 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 27 describes the external memory interface signals. Figure 17.
External Bus Cycles This section describes the bus cycles the AT8xC51SND1C executes to read (see Figure 18), and write data (see Figure 19) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the Section “X2 Feature”, page 12. Slow peripherals can be accessed by stretching the read and write cycles.
AT8xC51SND1C Dual Data Pointer Description The AT8xC51SND1C implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 21) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 20). Figure 20.
Registers Table 28. PSW Register PSW (S:8Eh) – Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0 4-3 RS1:0 Register Bank Select Bits Refer to Table 25 for bits description. 2 OV Overflow Flag Overflow set by arithmetic operations.
AT8xC51SND1C Table 29. AUXR Register AUXR (S:8Eh) – Auxiliary Control Register 7 6 5 4 3 2 1 0 - EXT16 M0 DPHDIS XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 EXT16 5 M0 External Memory Access Stretch Bit Set to stretch RD or WR signals duration to 15 CPU clock periods. Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
Special Function Registers The Special Function Registers (SFRs) of the AT8xC51SND1C derivatives fall into the categories detailed in Table 30 to Table 46. The relative addresses of these SFRs are provided together with their reset values in Table 47. In this table, the bit-addressable registers are identified by Note 1. Table 30.
AT8xC51SND1C Table 34. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 8-bit Port 4 P5 D8h 4-bit Port 5 7 6 5 4 3 2 1 0 - - - - 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Table 35. Flash Memory SFR Mnemonic Add Name FCON(1) Note: D1h Flash Control 1. FCON register is only available in AT89C51SND1C product. Table 36.
Table 37.
AT8xC51SND1C Table 39.
Table 42. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 92h Baud Rate Control BRL 91h Baud Rate Reload 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI BRR TBCK RBCK SPD SRC Table 43.
AT8xC51SND1C Table 47.
Interrupt System The AT8xC51SND1C, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND1C activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard).
AT8xC51SND1C Table 49. Priority Levels IPHxx IPLxx Priority Level 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by an internal hardware polling sequence detailed in Table 50.
Figure 21. Interrupt Control System INT0 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1 External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.2 Timer 1 ET1 TXD RXD Serial Port 00 01 10 11 IEN0.3 ES MP3 Decoder 00 01 10 11 IEN0.4 EMP3 Audio Interface 00 01 10 11 IEN0.5 EAUD MCLK MDAT MCMD MMC Controller 00 01 10 11 IEN0.6 EMMC SCL SDA TWI Controller 00 01 10 11 IEN1.0 EI2C SCK SI SO SPI Controller 00 01 10 11 IEN1.
AT8xC51SND1C External Interrupts INT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in Figure 22. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON register.
Registers Table 51. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0 7 6 5 4 3 2 1 0 EA EAUD EMP3 ES ET1 EX1 ET0 EX0 Bit Number 7 Bit Mnemonic Description EA Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EAUD Audio Interface Interrupt Enable Bit Set to enable audio interface interrupt.
AT8xC51SND1C Table 52. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register 1 7 6 5 4 3 2 1 0 - EUSB - EKB EADC ESPI EI2C EMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 EUSB 5 - 4 EKB 3 EADC A to D Converter Interrupt Enable Bit Set to enable ADC interrupt. Clear to disable ADC interrupt. 2 ESPI SPI Controller Interrupt Enable Bit Set to enable SPI interrupt. Clear to disable SPI interrupt.
Table 53. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0 7 6 5 4 3 2 1 0 - IPHAUD IPHMP3 IPHS IPHT1 IPHX1 IPHT0 IPHX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 IPHAUD Audio Interface Interrupt Priority Level MSB Refer to Table 49 for priority level description. 5 IPHMP3 MP3 Decoder Interrupt Priority Level MSB Refer to Table 49 for priority level description.
AT8xC51SND1C Table 54. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1 7 6 5 4 3 2 1 0 - IPHUSB - IPHKB IPHADC IPHSPI IPHI2C IPHMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 IPHUSB 5 - 4 IPHKB 3 IPHADC A to D Converter Interrupt Priority Level MSB Refer to Table 49 for priority level description. 2 IPHSPI SPI Interrupt Priority Level MSB Refer to Table 49 for priority level description.
Table 55. IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register 0 7 6 5 4 3 2 1 0 - IPLAUD IPLMP3 IPLS IPLT1 IPLX1 IPLT0 IPLX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 IPLAUD Audio Interface Interrupt Priority Level LSB Refer to Table 49 for priority level description. 5 IPLMP3 MP3 Decoder Interrupt Priority Level LSB Refer to Table 49 for priority level description.
AT8xC51SND1C Table 56. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - IPLUSB - IPLKB IPLADC IPLSPI IPLI2C IPLMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 IPLUSB 5 - 4 IPLKB 3 IPLADC A to D Converter Interrupt Priority Level LSB Refer to Table 49 for priority level description. 2 IPLSPI SPI Interrupt Priority Level LSB Refer to Table 49 for priority level description.
Power Management 2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12. Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin.
AT8xC51SND1C Table 58. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) VDD Rise Time Oscillator Start-Up Time 1 ms 10 ms 100 ms 5 ms 820 nF 1.2 µF 12 µF 20 ms 2.7 µF 3.9 µF 12 µF Note: 1. These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
Entering Idle Mode To enter Idle mode, the user must set the IDL bit in PCON register (see Table 59). The AT8xC51SND1C enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: Exiting Idle Mode If IDL bit and PD bit are set simultaneously, the AT8xC51SND1C enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. There are 2 ways to exit Idle mode: 1. Generate an enabled interrupt.
AT8xC51SND1C resumes when the input is released (see Figure 26) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 27). This behavior is necessary for decoding the key while it is still pressed. In both cases, execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode.
Registers Table 59. PCON Register PCON (S:87h) – Power Configuration Register 7 6 5 4 3 2 1 0 - - - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. 7-4 - 3 GF1 General-purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
AT8xC51SND1C Timers/Counters The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
Figure 28. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK 0 Timer 0 Clock PER CLOCK 0 Timer 1 Clock 1 OSC CLOCK 1 OSC CLOCK ÷2 T0X2 T1X2 CKCON.1 CKCON.2 TIM0 CLOCK TIM1 CLOCK Timer 0 Clock Symbol Timer 0 ÷2 Timer 1 Clock Symbol Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 29 through Figure 35 show the logical configuration of each mode.
AT8xC51SND1C Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 31). The selected input increments TL0 register. Figure 32 gives the overflow period calculation formula when in timer mode. Figure 31. Timer/Counter x (x = 0 or 1) in Mode 1 TIMx CLOCK ÷6 0 THx (8 bits) 1 TLx (8 bits) Overflow TFx TCON Reg Tx Timer x Interrupt Request C/Tx# TMOD Reg INTx GATEx TRx TMOD Reg TCON Reg Figure 32.
3. Figure 34 gives the autoreload period calculation formulas for both TF0 and TF1 flags. Figure 35. Timer/Counter 0 in Mode 3: 2 8-bit Counters TIM0 CLOCK ÷6 0 1 TL0 (8 bits) Overflow TH0 (8 bits) Overflow TF0 TCON.5 T0 Timer 0 Interrupt Request C/T0# TMOD.2 INT0 GATE0 TR0 TMOD.3 TIM0 CLOCK TCON.4 ÷6 TF1 TCON.7 Timer 1 Interrupt Request TR1 TCON.6 Figure 36.
AT8xC51SND1C Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 29). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 31). The selected input increments TL1 register.
Registers Table 60. TCON Register TCON (S:88h) – Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
AT8xC51SND1C Table 61. TMOD Register TMOD (S:89h) – Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Bit Number Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
Table 63. TL0 Register TL0 (S:8Ah) – Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 64. TH1 Register TH1 (S:8Dh) – Timer 1 High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 High Byte of Timer 1 Reset Value = 0000 0000b Table 65.
AT8xC51SND1C Watchdog Timer The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 38, the 14-bit prescaler is fed by the WDT clock detailed in Section “Watchdog Clock Controller”, page 59.
Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset the application (refer to Section “Power Management”, page 46).
AT8xC51SND1C Registers Table 67. WDTRST Register WDTRST (S:A6h Write only) – Watchdog Timer Reset Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - Watchdog Control Value Reset Value = XXXX XXXXb Figure 41. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Program Register 7 6 5 4 3 2 1 0 - - - - - WTO2 WTO1 WTO0 Bit Number Bit Mnemonic Description 7-3 - 2-0 WTO2:0 Reserved The value read from these bits is indeterminate.
MP3 Decoder The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be encoded into only 2.
AT8xC51SND1C MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in its input buffer(1). In order to manage the load of MP3 data in the frame buffer, a hardware handshake consisting of data request and data acknowledgment is implemented. Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as explained in Section “Interrupt”.
Audio Controls Volume Control The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 69. Table 69. Volume Control Equalization Control VOL4:0 or VOR4:0 Volume Gain (dB) 00000 Mute 00001 -33 00010 -27 11110 -1.5 11111 0 Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium band from 750 Hz to 3300 Hz and a treble band over 3300 Hz.
AT8xC51SND1C Frame Information The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. MPVER and MPFS1:0 bits allow decoding of the sampling frequency according to Table 71. MPVER bit gives the MPEG version (2 or 1). Table 71. MP3 Frame Frequency Sampling Ancillary Data MPVER MPFS1 MPFS0 Fs (kHz) 0 0 0 22.
Interrupt Description As shown in Figure 46, the MP3 decoder implements five interrupt sources reported in ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register. All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY, MSKREQ, and MSKANC mask bits respectively in MP3CON register. The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
AT8xC51SND1C Figure 47. MP3 Interrupt Service Routine Flow MP3 Decoder ISR Read MP3STA Data Request? MPFREQ = 1? Data Request Handler Write MP3 Data to MP3DAT Ancillary Data?(1) MPANC = 1? Ancillary Data Handler Sync Error?(1) ERRSYN = 1? Read ANN2:0 Ancillary Bytes From MP3ANC Synchro Error Handler Reload MP3 Frame Through MP3DAT Layer Error?(1) ERRSYN = 1? Layer Error Handler CRC Error Handler Load New MP3 Frame Through MP3DAT Note: 1. Test these bits only if needed (unmasked interrupt).
Registers Table 72. MP3CON Register MP3CON (S:AAh) – MP3 Decoder Control Register 7 6 5 4 3 2 1 0 MPEN MPBBST CRCEN MSKANC MSKREQ MSKLAY MSKSYN MSKCRC Bit Number Bit Mnemonic Description MP3 Decoder Enable Bit Set to enable the MP3 decoder. Clear to disable the MP3 decoder. 7 MPEN 6 MPBBST Bass Boost Bit Set to enable the bass boost sound effect. Clear to disable the bass boost sound effect. 5 CRCEN CRC Check Enable Bit Set to enable processing of frame that contains CRC error.
AT8xC51SND1C Table 73. MP3STA Register MP3STA (S:C8h Read Only) – MP3 Decoder Status Register 7 6 5 4 3 2 1 0 MPANC MPREQ ERRLAY ERRSYN ERRCRC MPFS1 MPFS0 MPVER Bit Number Bit Mnemonic Description 7 MPANC Ancillary Data Available Flag Set by hardware as soon as one ancillary data is available (buffer not empty). Cleared by hardware when no more ancillary data is available (buffer empty). 6 MPREQ MP3 Data Request Flag Set by hardware when MP3 decoder request data.
Table 75. MP3STA1 Register MP3STA1 (S:AFh) – MP3 Decoder Status Register 1 7 6 5 4 3 2 1 0 - - - MPFREQ MPFREQ - - - Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. 7-5 - 4 MPFREQ MP3 Frame Data Request Flag Set by hardware when MP3 decoder request data. Cleared when MP3 decoder no more request data . 3 MPBREQ MP3 Byte Data Request Flag Set by hardware when MP3 decoder request data. Cleared when writing to MP3DAT.
AT8xC51SND1C Table 78. MP3VOR Register MP3VOR (S:9Fh) – MP3 Volume Right Control Register 7 6 5 4 3 2 1 0 - - - VOR4 VOR3 VOR2 VOR1 VOR0 Bit Number Bit Mnemonic Description 7-5 - Reserved The value read from these bits is always 0. Do not set these bits. 4-0 VOR4:0 Volume Right Value Refer to Table 69 for the right channel volume control description. Reset Value = 0000 0000b Table 79.
Table 81. MP3TRE Register MP3TRE (S:B6h) – MP3 Treble Control Register 7 6 5 4 3 2 1 0 - - TRE5 TRE4 TRE3 TRE2 TRE1 TRE0 Bit Number Bit Mnemonic Description 7-6 - 5-0 TRE5:0 Reserved The value read from these bits is always 0. Do not set these bits. Treble Gain Value Refer to Table 70 for the treble control description. Reset Value = 0000 0000b Table 82.
AT8xC51SND1C Audio Output Interface The AT8xC51SND1C implement an audio output interface allowing the audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 12) allows connection of almost all of the commercial audio DAC families available on the market.
Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 49 shows the audio interface clock generator and its calculation formula. The audio interface clock frequency depends on the incoming MP3 frames and the audio DAC used. Figure 49.
AT8xC51SND1C Figure 51. Audio Output Format DSEL DCLK DOUT Left Channel 1 2 3 Right Channel 13 14 15 LSB MSB B14 16 B1 1 2 3 13 14 15 LSB MSB B14 16 B1 I2S Format with DSIZ = 0 and JUST4:0 = 00001. DSEL DCLK Left Channel 1 DOUT 2 Right Channel 3 17 MSB B14 LSB 18 32 1 2 3 17 MSB B14 LSB 18 32 I2S Format with DSIZ = 1 and JUST4:0 = 00001.
Table 83. Sample Duplication Factor DUP1 DUP0 Factor 0 0 No sample duplication, DAC rate = 8 kHz (C51 rate). 0 1 One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 1 0 2 samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate). MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer.
AT8xC51SND1C Figure 53. MP3 Mode Audio Configuration Flow MP3 Mode Configuration Program Audio Clock Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb SRC = 0 Voice or Sound Playing Enable DAC System Clock AUDEN = 1 Wait For DAC Set-up Time Enable Data Request DRQEN = 1 In voice or sound playing mode, the operations required are to configure the PLL and the audio interface according to the DAC selected.
Registers Table 84. AUDCON0 Register AUDCON0 (S:9Ah) – Audio Interface Control Register 0 7 6 5 4 3 2 1 0 JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR Bit Number Bit Mnemonic Description Audio Stream Justification Bits Refer to Section "Data Converter", page 74 for bits description. 7-3 JUST4:0 2 POL DSEL Signal Output Polarity Set to output the left channel on high level of DSEL output (PCM mode). Clear to output the left channel on the low level of DSEL output (I2S mode).
AT8xC51SND1C Table 86. AUDSTA Register AUDSTA (S:9Ch Read Only) – Audio Interface Status Register 7 6 5 4 3 2 1 0 SREQ UDRN AUBUSY - - - - - Bit Number Bit Mnemonic Description SREQ Audio Sample Request Flag Set in C51 audio source mode when the audio interface request samples (buffer half empty). This bit generates an interrupt if not masked and if enabled in IEN0. Cleared by hardware when samples are loaded in AUDDAT.
Universal Serial Bus The AT8xC51SND1C implements a USB device controller supporting full speed data transfer.
AT8xC51SND1C Description The USB device controller provides the hardware that the AT8xC51SND1C needs to interface a USB link to a data flow stored in a double port memory. It requires a 48 MHz reference clock provided by the clock controller as detailed in Section "Clock Controller", page 81. This clock is used to generate a 12 MHz Full Speed bit clock from the received USB differential data flow and to transmit data according to full speed USB device tolerance.
Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC generation and checking. • ACKs and NACKs automatic generation. • TOKEN type identifying. • Address checking. • Clock recovery (using DPLL). Figure 57.
AT8xC51SND1C Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT8xC51SND1C and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 59 shows typical USB IN and OUT transactions reporting the split in the hardware (UFI) and software (C51) load. Figure 58.
Configuration General Configuration • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” on page 19). The USB controller should be then enabled by setting the EUSB bit in the USBCON register. • Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allow the USB controller to answer to the requests sent at the address 0.
AT8xC51SND1C • Endpoint enable Before using an endpoint, this must be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. • Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode.
• Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the Byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register.
AT8xC51SND1C Bulk/Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. Bulk/Interrupt OUT Transactions in Standard Mode Figure 62.
Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 63.
AT8xC51SND1C If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Bulk/Interrupt IN Transactions in Standard Mode Figure 64.
Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 65.
AT8xC51SND1C Control Transactions Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled.
Isochronous Transactions Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corre Bulk-outsponding endpoint, store the number of data Bytes by reading the UBYCTX register.
AT8xC51SND1C If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochronous packets.
Miscellaneous USB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints.
AT8xC51SND1C Suspend/Resume Management Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.
Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value should be 0 in the other cases.
AT8xC51SND1C USB Interrupt System Interrupt System Priorities D+ D- Figure 68. USB Interrupt Control System 00 01 10 11 USB Controller EUSB EA IE1.6 IE0.7 IPH/L Priority Enable Interrupt Enable Lowest Priority Interrupts Table 1. Priority Levels USB Interrupt Control System IPHUSB IPLUSB USB Priority Level 0 0 0..................Lowest 0 1 1 1 0 2 1 1 3..................
Figure 69. USB Interrupt Control Block Diagram Endpoint X (X = 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPSTAX.6 UEPINT.X RXSETUP EPXIE UEPSTAX.2 UEPIEN.X STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU EUSB USBINT.5 EWUPCPU IE1.6 USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.
AT8xC51SND1C Registers Table 90. USBCON Register USBCON (S:BCh) – USB Global Control Register 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP - UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description 7 USBE USB Enable Bit Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controllor clock inputs.
Table 91. USBADDR Register USBADDR (S:C6h) – USB Address Register 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic Description 7 FEN Function Enable Bit Set to enable the function. The device firmware should set this bit after it has received a USB reset and participate in the following configuration process with the default address (FEN is reset to 0). Cleared by hardware at power-up, should not be cleared by the device firmware once set.
AT8xC51SND1C Table 93. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register 7 6 5 4 3 2 1 0 - - EWUPCPU EEORINT ESOFINT - - ESPINT Bit Number 7-6 5 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt Enable Bit EWUPCPU Set to enable the Wake Up CPU interrupt. Clear to disable the Wake Up CPU interrupt. 4 EEOFINT End Of Reset Interrupt Enable Bit Set to enable the End Of Reset interrupt.
Table 95. UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Bit Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 should always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear to disable the endpoint according to the device configuration.
AT8xC51SND1C Table 96. UEPSTAX Register UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTB0 TXCMP Bit Number Bit Mnemonic Description Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise. 7 6 DIR RXOUTB1 Note: This bit should be configured on RXSETUP interrupt before any other bit is changed.
Bit Number 5 4 3 2 1 0 Bit Mnemonic Description STALLRQ Stall Handshake Request Bit Set to send a STALL answer to the host for the next handshake. Clear otherwise. TXRDY TX Packet Ready Control Bit Set after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint FIFO only after this bit has been cleared.
AT8xC51SND1C Table 97. UEPRST Register UEPRST (S:D5h) – USB Endpoint FIFO Reset Register 7 6 5 4 3 2 1 0 - - - - - EP2RST EP1RST EP0RST Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. 7-3 - 2 EP2RST Endpoint 2 FIFO Reset Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received.
Table 99. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - - EP2INTE EP1INTE EP0INTE Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. 7-3 - 2 EP2INTE Endpoint 2 Interrupt Enable Bit Set to enable the interrupts for endpoint 2. Clear this bit to disable the interrupts for endpoint 2. 1 EP1INTE Endpoint 1 Interrupt Enable Bit Set to enable the interrupts for the endpoint 1.
AT8xC51SND1C Table 101. UBYCTX Register UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 - BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 Bit Number Bit Mnemonic Description 7 - 6-0 BYCT7:0 Reserved The value read from this bits is always 0. Do not set this bit. Byte Count Byte count of a received data packet. This Byte count is equal to the number of data Bytes received after the Data PID. Reset Value = 0000 0000b Table 102.
Table 103. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register 7 6 5 4 3 2 1 0 - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 Bit Number 7-3 5 Bit Mnemonic Description - CRCOK Reserved The value read from these bits is always 0. Do not set these bits. Frame Number CRC OK Bit Set by hardware after a non corrupted Frame Number in Start of Frame Packet is received. Updated after every Start Of Frame packet reception.
AT8xC51SND1C MultiMedia Card Controller The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. Card Concept The basic MultiMedia Card concept is based on transferring data via a minimum number of signals.
Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system. The bus lines can be divided into three groups: Bus Protocol • Power supply: VSS1 and VSS2, VDD – used to supply the cards. • Data transfer: MCMD, MDAT – used for bi-directional communication. • Clock: MCLK – used to synchronize data transfer across the bus.
AT8xC51SND1C Figure 71. (Multiple) Block Read Operation Stop Command MCMD Command Response MDAT Command Response Data Block CRC Data Block CRC Data Block CRC Block Read Operation Data Stop Operation Multiple Block Read Operation As shown in Figure 72 and Figure 73 the data write operation uses a simple busy signalling of the write operation duration on the data line (MDAT). Figure 72.
Table 105. Command Token Format Bit Position 47 46 45:40 39:8 7:1 0 Width (Bits) 1 1 6 32 7 1 Value ‘0’ ‘1’ - - - ‘1’ Start bit Transmission bit Command Index Argument CRC7 End bit Description Response Token Format There are five types of response tokens (R1 to R5). As shown in Figure 76, responses have a code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line.
AT8xC51SND1C Table 108. R3 Response Format (OCR Register) Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (bits) 1 1 6 32 7 1 Value ‘0’ ‘0’ ‘111111’ - ‘1111111’ ‘1’ Start bit Transmission bit Reserved OCR register Reserved End bit Description Table 109.
required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Following is a list of the various bus transactions: Description • A command with no response. 8 clocks after the host command End bit. • A command with response. 8 clocks after the card command End bit. • A read data transaction. 8 clocks after the End bit of the last data block. • A write data transaction. 8 clocks after the CRC status token.
AT8xC51SND1C Figure 79. MMC Clock Generator and Symbol OSC CLOCK Controller Clock OSCclk MMCclk = ----------------------------MMCD + 1 MMCLK MMCEN MMCON2.7 MMCD7:0 MMC Clock MMC CLOCK MMC Clock Symbol As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The MMC command and data clock is generated on MCLK output and sent to the command line and data line controllers. Figure 80 shows the MMC controller configuration flow.
Command Line Controller As shown in Figure 81, the command line controller is divided in 2 channels: the command transmitter channel that handles the command transmission to the card through the MCMD line and the command receiver channel that handles the response reception from the card through the MCMD line. These channels are detailed in the following sections. Figure 81. Command Line Controller Block Diagram TX Pointer CTPTR MMCON0.
AT8xC51SND1C User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register which resets the write pointer to the transmit FIFO. Figure 82. Command Transmission Flow Command Transmission Configure Response RESPEN = X RFMT = X CRCDIS = X Load Command in Buffer MMCMD = index MMCMD = argument Transmit Command CMDEN = 1 CMDEN = 0 Command Receiver The end of the response reception is signalled to you by the EORI flag in MMINT register.
Data Line Controller The data line controller is based on a 16-Byte FIFO used both by the data transmitter channel and by the data receiver channel. Figure 83. Data Line Controller Block Diagram MMINT.0 MMINT.2 MMSTA.3 MMSTA.4 F1EI F1FI DATFS CRC16S CRC16 and Format Checker Data Converter Serial -> // 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 RX Pointer DRPTR MMCON0.7 16-Byte FIFO MMDAT MCBI CBUSY MMINT.1 MMSTA.5 MDAT Data Converter // -> Serial CRC16 Generator 8-Byte MMINT.
AT8xC51SND1C Figure 84. Data Controller Configuration Flows Data Stream Configuration Data Single Block Configuration Data Multi-Block Configuration Configure Format DFMT = 0 Configure Format DFMT = 1 MBLOCK = 0 BLEN3:0 = XXXXb Configure Format DFMT = 1 MBLOCK = 1 BLEN3:0 = XXXXb Data Transmitter Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register.
Figure 85.
AT8xC51SND1C Figure 86.
This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). Data Reading Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Figure 87.
AT8xC51SND1C Figure 88. Data Block Reception Flows Data Block Reception Data Block Initialization Data Block Reception ISR Start Transmission DATEN = 1 DATEN = 0 Unmask FIFOs Full F1FM = 0 F2FM = 0 FIFO Full? F1EI or F2EI = 1? FIFO Full? F1EI or F2EI = 1? Start Transmission DATEN = 1 DATEN = 0 FIFO Reading read 8 data from MMDAT No More Data To Receive? FIFO Reading read 8 data from MMDAT Mask FIFOs Full F1FM = 1 F2FM = 1 No More Data To Receive? a. Polling mode Flow Control b.
Interrupt Description As shown in Figure 89, the MMC controller implements eight interrupt sources reported in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags are detailed in the previous sections. All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM, and F2EM mask bits respectively in MMMSK register.
AT8xC51SND1C Registers Table 112. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register 0 7 6 5 4 3 2 1 0 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7 DRPTR Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. 6 DTPTR Data Transmit Pointer Reset Bit Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO.
Table 113. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register 1 7 6 5 4 3 2 1 0 BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN Bit Number Bit Mnemonic Description 7-4 BLEN3:0 Block Length Bits Refer to Table 111 for bits description. Do not program value > 1011b 3 DATDIR Data Direction Bit Set to select data transfer from host to card (write mode). Clear to select data transfer from card to host (read mode).
AT8xC51SND1C Table 115. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register 7 6 5 4 3 2 1 0 - - CBUSY CRC16S DATFS CRC7S RESPFS CFLCK Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. 7-6 - 5 CBUSY Card Busy Flag Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line.
Table 116. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 7 6 5 4 3 2 1 0 MCBI EORI EOCI EOFI F2FI F1FI F2EI F1EI Bit Number Bit Mnemonic Description 7 MCBI MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). Cleared when reading MMINT. 6 EORI End of Response Interrupt Flag Set by hardware at the end of response reception. Cleared when reading MMINT.
AT8xC51SND1C Table 117. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register 7 6 5 4 3 2 1 0 MCBM EORM EOCM EOFM F2FM F1FM F2EM F1EM Bit Number Bit Mnemonic Description 7 MCBM MMC Card Busy Interrupt Mask Bit Set to prevent MCBI flag from generating an MMC interrupt. Clear to allow MCBI flag to generate an MMC interrupt. 6 EORM End Of Response Interrupt Mask Bit Set to prevent EORI flag from generating an MMC interrupt. Clear to allow EORI flag to generate an MMC interrupt.
Table 119. MMDAT Register MMDAT (S:DCh) – MMC Data Register 7 6 5 4 3 2 1 0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit Number 7-0 Bit Mnemonic Description MD7:0 MMC Data Byte Input (write) or output (read) register of the data FIFO. Reset Value = 1111 1111b Table 120.
AT8xC51SND1C IDE/ATAPI Interface The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16bit data transfer (read or write) between the AT8xC51SND1C and the IDE device. Description The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 29, page 29). As soon as this bit is set, all MOVX instructions read or write are done in a 16bit mode compare to the standard 8-bit mode.
Figure 91. IDE Write Waveforms CPU Clock ALE WR(1) P0 P2 Notes: IDE Device Connection P2 DPL or Ri D7:0 DPH or P2(2),(3) D15:8 P2 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH. Figure 92 and Figure 93 show 2 examples on how to interface up to 2 IDE devices to the AT8xC51SND1C.
AT8xC51SND1C Table 121. External Data Memory Interface Signals Registers Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the IDE interface. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information is available on lines AD7:0.
Serial I/O Port The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition.
AT8xC51SND1C Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 95 the Internal Baud Rate Generator is an 8-bit auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register (see Table 129). The Internal Baud Rate Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate.
Figure 97. Transmission Waveforms (Mode 0) TXD Write to SBUF RXD D0 D1 D2 D3 D4 D5 D6 D7 TI Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 98, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight samplings, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception.
AT8xC51SND1C Asynchronous Modes (Modes 1, 2 and 3) The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 101 shows the Serial Port block diagram in such asynchronous modes. Figure 101. Serial I/O Port Block Diagram (Modes 1, 2 and 3) SCON.6 SCON.7 SCON.3 SM1 SM0 TB8 Mode Decoder SBUF Tx SR TXD Rx SR RXD M3 M2 M1 M0 T1 CLOCK Mode & Clock Controller IBRG CLOCK SBUF Rx PER CLOCK Mode 1 RB8 SCON.2 SM2 TI RI SCON.4 SCON.1 SCON.
Framing Error Detection (Modes 1, 2 and 3) Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 104. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in SCON register.
AT8xC51SND1C Table 124. Internal Baud Rate Generator Value FPER = 6 MHz(1) FPER = 8 MHz(1) FPER = 10 MHz(1) Baud Rate SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % 115200 - - - - - - - - - - - - 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.
Figure 108. Baud Rate Formula (Mode 2) Baud_Rate= Multiprocessor Communication (Modes 2 and 3) 2SMOD1 ⋅ FPER 32 Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set).
AT8xC51SND1C The following is an example of how to use given addresses to address different slaves: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0010b SADEN = 1111 1101b Given = 1111 00X1b The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.
Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 109 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
AT8xC51SND1C Registers Table 125. SCON Register SCON (S:98h) – Serial Control Register 7 6 5 4 3 2 1 0 FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description FE 7 Framing Error Bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. SM0 Serial Port Mode Bit 0 Refer to Table 123 for mode selection. SM1 Serial Port Mode Bit 1 Refer to Table 123 for mode selection.
Table 126. SBUF Register SBUF (S:99h) – Serial Buffer Register 7 6 5 4 3 2 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Bit Number 7-0 Bit Mnemonic Description SD7:0 Serial Data Byte Read the last data received by the serial I/O Port. Write the data to be transmitted by the serial I/O Port. Reset value = XXXX XXXXb Table 127.
AT8xC51SND1C Table 129. BDRCON Register BDRCON (S:92h) – Baud Rate Generator Control Register 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD M0SRC Bit Number Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. 7-5 - 4 BRR Baud Rate Run Bit Set to enable the baud rate generator. Clear to disable the baud rate generator. 3 TBCK Transmission Baud Rate Selection Bit Set to select the baud rate generator as transmission baud rate generator.
Synchronous Peripheral Interface The AT8xC51SND1C implements a Synchronous Peripheral Interface with master and slave modes capability. Figure 111 shows an SPI bus configuration using the AT8xC51SND1C as master connected to slave peripherals while Figure 112 shows an SPI bus configuration using the AT8xC51SND1C as slave of an other master.
AT8xC51SND1C Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 132); SPSTA, the SPI status register (see Table 133); and SPDAT, the SPI data register (see Table 134). Master Mode The SPI operates in master mode when the MSTR bit in SPCON is set. Figure 113 shows the SPI block diagram in master mode. Only a master SPI module can initiate transmissions. Software begins the transmission by writing to SPDAT.
Slave Mode The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded in SPDAT. Figure 114 shows the SPI block diagram in slave mode. In slave mode, before a data transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must remain low until the transmission of the Byte is complete.
AT8xC51SND1C Table 131. Serial Bit Rates Bit Rate (kHz) Vs FPER SPR1 SPR0 0 0 0 3000 4000 5000 6000 8000 10000 2 0 0 1 1500 2000 2500 3000 4000 5000 4 0 1 0 750 1000 1250 1500 2000 2500 8 0 1 1 375 500 625 750 1000 1250 16 1 0 0 187.5 250 312.5 375 500 625 32 1 0 1 93.75 125 156.25 187.5 250 312.5 64 1 1 0 46.875 62.5 78.125 93.75 125 156.25 128 1 1 1 6000 8000 10000 12000 16000 20000 1 FPER Divider 1.
Figure 116. Data Transmission Format (CPHA = 1) 1 2 3 4 5 6 7 8 MOSI (from master) MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB MISO (from slave) MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) LSB SS (to slave) Capture point SS Management Figure 115 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB capture point.
AT8xC51SND1C Interrupt The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault” flags. As shown in Figure 118, these flags are combined toghether to appear as a single interrupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out and is cleared by reading SPSTA and then reading from or writing to SPDAT. The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and then writing to SPCON.
Configuration The SPI configuration is made through SPCON. Master Configuration The SPI operates in master mode when the MSTR bit in SPCON is set. Slave Configuration The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded is SPDAT.
AT8xC51SND1C Master Mode with Interrupt Figure 120 shows the initialization phase and the transfer phase flows using the interrupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 131. The transfer format depends on the slave peripheral. SS may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. Figure 120.
Slave Mode with Polling Policy Figure 121 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of reception” check). This provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the process may then be interrupted at any time by higher priority tasks. Figure 121.
AT8xC51SND1C Slave Mode with Interrupt Policy Figure 120 shows the initialization phase and the transfer phase flows using the interrupt. The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. Figure 122.
Registers Table 132. SPCON Register SPCON (S:C3h) – SPI Control Register 7 6 5 4 3 2 1 0 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic Description 7 SPR2 SPI Rate Bit 2 Refer to Table 131 for bit rate description. 6 SPEN SPI Enable Bit Set to enable the SPI interface. Clear to disable the SPI interface. 5 SSDIS Slave Select Input Disable Bit Set to disable SS in both master and slave modes. In slave mode this bit has no effect if CPHA = 0.
AT8xC51SND1C Table 133. SPSTA Register SPSTA (S:C4h) – SPI Status Register 7 6 5 4 3 2 1 0 SPIF WCOL - MODF - - - - Bit Number Bit Mnemonic Description 7 SPIF 6 WCOL 5 - 4 MODF 3-0 - SPI Interrupt Flag Set by hardware when an 8-bit shift is completed. Cleared by hardware when reading or writing SPDAT after reading SPSTA. Write Collision Flag Set by hardware to indicate that a collision has been detected. Cleared by hardware to indicate that no collision has been detected.
Two-wire Interface (TWI) Controller The AT8xC51SND1C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling where the AT8xC51SND1C is used as a peripheral of a host. The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for simple but efficient integrated circuit control.
AT8xC51SND1C Figure 124. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 2 R/W ACK direction signal bit from receiver 8 Nth data Byte 9 S 1 2 ACK signal from receiver 8 9 Clock Line Held Low While Serial Interrupts Are Serviced P/S The four operating modes are: • Master transmitter • Master receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation are shown in Figure 125 through Figure 128.
Bit Rate The bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 142). The predefined bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate generator is based on timer 1 overflow output. Table 135.
AT8xC51SND1C Master Receiver Mode In the master receiver mode, a number of data Bytes are received from a slave transmitter (see Figure 126). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before the serial transfer can continue.
Slave Transmitter Mode In the slave transmitter mode, a number of data Bytes are transmitted to a master receiver (see Figure 128). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (R) for operating in the slave transmitter mode.
AT8xC51SND1C Figure 125.
Figure 126.
AT8xC51SND1C Figure 127. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes.
Figure 128. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. S SLA R A Data A8h Arbitration lost as master and addressed as slave A B8h Data A P or S C0h A B0h Last data Byte transmitted. Switched to not addressed slave (SSAA = 0).
AT8xC51SND1C Table 136.
Table 137. Status for Master Receiver Mode Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT SSSTA SSSTO SSI SSAA X 0 0 X X 0 0 X X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode. 0 0 0 X TWI bus will be released and not addressed slave mode will be entered. 1 0 0 X A START condition will be transmitted when the bus becomes free.
AT8xC51SND1C Table 138. Status for Slave Receiver Mode with Own Slave Address Application Software Response Status Code SSSTA 60h 68h 80h To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT SSSTA SSSTO SSI SSAA Own SLA+W has been received; ACK has been returned No SSDAT action X 0 0 0 Data Byte will be received and NOT ACK will be returned. No SSDAT action X 0 0 1 Data Byte will be received and ACK will be returned.
Table 139.
AT8xC51SND1C Table 140. Status for Slave Transmitter Mode Application Software Response Status Code SSSTA A8h B0h B8h Status of the TWI Bus and TWI Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Own SLA+R has been received; ACK has been returned Write data Byte X 0 0 0 Last data Byte will be transmitted. Write data Byte X 0 0 1 Data Byte will be transmitted.
Registers Table 142. SSCON Register SSCON (S:93h) – Synchronous Serial Control Register 7 6 5 4 3 2 1 0 SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 Bit Number Bit Mnemonic Description Synchronous Serial Control Rate Bit 2 Refer to Table 135 for rate description. 7 SSCR2 6 SSPE Synchronous Serial Peripheral Enable Bit Set to enable the controller. Clear to disable the controller. 5 SSSTA Synchronous Serial Start Flag Set to send a START condition on the bus.
AT8xC51SND1C Table 143. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register 7 6 5 4 3 2 1 0 SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 Bit Number Bit Mnemonic Description 7:3 SSC4:0 2:0 0 Synchronous Serial Status Code Bits 0 to 4 Refer to Table 136 to Table 128 for status description. Always 0. Reset Value = F8h Table 144.
Analog to Digital Converter The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling at 8 kHz.
AT8xC51SND1C Clock Generator The ADC clock is generated by division of the peripheral clock (see details in section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 131 shows the ADC clock generator and its calculation formula(1). Figure 131. ADC Clock Generator and Symbol Caution: ADCLK PER CLOCK ÷2 ADCD4:0 ADC CLOCK ADC Clock ADC Clock Symbol PERclk ADCclk = ------------------------2 ⋅ ADCD Note: 1.
Figure 132. ADC Configuration Flow ADC Configuration Program ADC Clock ADCD4:0 = xxxxxb Enable ADC ADIDL = x ADEN = 1 Wait Setup Time Conversion Launching The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set during the conversion. As soon as the conversion is started, it takes 11 clock periods (TCONV) before the data is available in ADDH and ADDL registers. Figure 133.
AT8xC51SND1C Registers Table 147. ADCON Register ADCON (S:F3h) – ADC Control Register 7 6 5 4 3 2 1 0 - ADIDL ADEN ADEOC ADSST - - ADCS Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 ADIDL ADC Pseudo-Idle Mode Set to suspend the CPU core activity (pseudo-idle mode) during conversion. Clear by hardware at the end of conversion. 5 ADEN ADC Enable Bit Set to enable the A to D converter.
Table 149. ADDH Register ADDH (S:F5h Read Only) – ADC Data High Byte Register 7 6 5 4 3 2 1 0 ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 Bit Number 7-0 Bit Mnemonic Description ADAT9:2 ADC Data 8 Most Significant Bits of the 10-bit ADC data. Reset Value = 0000 0000b Table 150.
AT8xC51SND1C Keyboard Interface The AT8xC51SND1C implement a keyboard interface allowing the connection of a 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.
Registers Table 151. KBCON Register KBCON (S:A3h) – Keyboard Control Register 7 6 5 4 3 2 1 0 KINL3 KINL2 KINL1 KINL0 KINM3 KINM2 KINM1 KINM0 Bit Number Bit Mnemonic Description 7-4 KINL3:0 Keyboard Input Level Bit Set to enable a high level detection on the respective KIN3:0 input. Clear to enable a low level detection on the respective KIN3:0 input. 3-0 KINM3:0 Keyboard Input Mask Bit Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
AT8xC51SND1C Electrical Characteristics Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS .................................... -0.3 *NOTICE: to +4.0 V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
Table 153. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min AT89C51SND1C Operating Current Typ(1) Max (3) X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 Units Test Conditions VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz IDD VDD < 3.3 V AT83C51SND1C Operating Current AT89C51SND1C TBD TBD (3) X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 Idle Mode Current mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz IDL VDD < 3.
AT8xC51SND1C IDD, IDL and IPD Test Conditions Figure 136. IDD Test Condition, Active Mode VDD VDD RST (NC) Clock Signal VDD PVDD UVDD AVDD X2 X1 IDD VDD P0 VSS PVSS UVSS AVSS VSS TST All other pins are unconnected Figure 137. IDL Test Condition, Idle Mode VDD RST VSS (NC) Clock Signal VDD PVDD UVDD AVDD X2 X1 IDL VDD P0 VSS PVSS UVSS AVSS VSS TST All other pins are unconnected Figure 138.
A to D Converter Table 155. A to D Converter DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Typ Max Units 3.3 V Test Conditions AVDD Analog Supply Voltage AIDD Analog Operating Supply Current 600 µA AVDD= 3.3V AIN1:0= 0 to AVDD ADEN= 1 AIPD Analog Standby Current 2 µA AVDD= 3.3V ADEN= 0 or PD= 1 AVIN Analog Input Voltage AVSS AVDD V Reference Voltage AREFN AREFP AVSS 2.4 AVDD 10 30 KΩ TA= 25°C 10 pF TA= 25°C AVREF RREF 2.
AT8xC51SND1C Phase Lock Loop Schematic Figure 140. PLL Filter Connection FILT R C2 C1 VSS Parameters VSS Table 157. PLL Filter Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF In System Programming Schematic Figure 141. ISP Pull-Down Connection ISP RISP VSS Parameters Table 158. ISP Pull-Down Characteristics VDD = 2.7 to 3.
AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 159. External 8-bit Bus Cycles Timing Symbol Definitions Signals Timings Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Test conditions: capacitive load on all pins= 50 pF. Table 160. External 8-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.
AT8xC51SND1C Table 161. External 8-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C Variable Clock Standard Mode Symbol Waveforms Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Variable Clock X2 Mode Max Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.
Figure 143. External 8-bit Bus Cycle - Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 162.
AT8xC51SND1C Timings Test conditions: capacitive load on all pins= 50 pF. Table 163. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.
Waveforms Figure 144. External IDE 16-bit Bus Cycle - Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 D15:8(1) A15:8 Data In Note: 1. D15:8 is written in DAT16H SFR. Figure 145. External IDE 16-bit Bus Cycle - Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 D15:8(1) Data Out Note: 1. D15:8 is the content of DAT16H SFR.
AT8xC51SND1C Timings Test conditions: capacitive load on all pins= 50 pF. Table 166. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period TCHCX 2 TPER Clock High Time 0.8 TPER TCLCX Clock Low Time 0.
Waveforms Figure 146. SPI Slave Waveforms (SSCPHA= 0) SS (input) TSLCH TSLCL TCHCH SCK (SSCPOL= 0) (input) TCHCX TCLCH TSHSL TCLCX TCHCL SCK (SSCPOL= 1) (input) TCLOX TCHOX TCLOV TCHOV TSLOV MISO (output) TCLSH TCHSH SLAVE MSB OUT BIT 6 TSHOX SLAVE LSB OUT (1) TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 147.
AT8xC51SND1C Figure 148. SPI Master Waveforms (SSCPHA= 0) SS (output) TCHCH SCK (SSCPOL= 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV MISO (output) Port Data Note: MSB OUT TCHOX BIT 6 LSB OUT Port Data 1. SS handled by software using general purpose port pin. Figure 149.
Two-wire Interface Timings Table 167. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT Min Max OUTPUT Min Max Start condition hold time 14·TCLCL(4) 4.0 µs(1) TLOW SCL low time 16·TCLCL(4) 4.7 µs(1) THIGH SCL high time 14·TCLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs -(2) TFC SCL fall time 0.3 µs 0.
AT8xC51SND1C MMC Interface Definition of symbols Table 168. MMC Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Table 169. MMC Interface AC timings VDD = 2.7 to 3.
Audio Interface Definition of symbols Table 170. Audio Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Table 171. Audio Interface AC timings VDD = 2.7 to 3.
AT8xC51SND1C Analog to Digital Converter Definition of symbols Table 172. Analog to Digital Converter Timing Symbol Definitions Signals Characteristics Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Table 173. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.
Figure 154. Analog to Digital Converter Characteristics Offset Gain Error Error Ge OSe Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer curve Example of an actual transfer curve 7 6 5 Center of a step 4 Integral non-linearity (ILe) 3 Differential non-linearity (DLe) 2 1 1 LSB (ideal) 0 0 1 2 3 4 5 6 7 AVIN (LSB ideal) 1018 1019 1020 1021 1022 1023 1024 Offset Error OSe Flash Memory Definition of symbols Table 174.
AT8xC51SND1C Waveforms Figure 155. FLASH Memory - ISP Waveforms RST TSVRL TRLSX ISP(1) Note: 1. ISP must be driven through a pull-down resistor (see Section “In System Programming”, page 185). Figure 156. FLASH Memory - Internal Busy Waveforms FBUSY bit TBHBL External Clock Drive and Logic Level References Definition of symbols Table 176. External Clock Timing Symbol Definitions Signals C Timings Conditions Clock H High L Low X No Longer Valid Table 177.
Figure 158. AC Testing Input/Output Waveforms INPUTS VDD - 0.5 0.45 V Note: OUTPUTS 0.7 VDD VIH min 0.3 VDD VIL max 1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 159. Float Waveforms VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Note: 200 Timing Reference Points VOH - 0.1 V VOL + 0.
AT8xC51SND1C Ordering Information Memory Size Supply Voltage Temperature Range Max Frequency AT89C51SND1C-ROTIL 64K Flash 3V Industrial 40 MHz TQFP80 Tray AT89C51SND1C-7HTIL 64K Flash 3V Industrial 40 MHz BGA81 Tray AT83SND1Cxxx -ROTIL 64K ROM 3V Industrial 40 MHz TQFP80 Tray AT83SND1Cxxx(1)-7HTIL 64K ROM 3V Industrial 40 MHz BGA81 Tray Part Number (1) Package(2) Packing AT80SND1C-ROTIL ROMless 3V Industrial 40 MHz TQFP80 Tray AT80SND1C-7HTIL ROMless 3V Industr
Package Information TQFP80 202 AT8xC51SND1C 4109E–8051–06/03
AT8xC51SND1C BGA81 203 4109E–8051–06/03
PLCC84 204 AT8xC51SND1C 4109E–8051–06/03
AT8xC51SND1C Datasheet Change Log for AT8xC51SND1C Changes from 4109D10/02 to 4109E-06/03 1. Additional information on AT83C51SND1C product. 2. Added BGA81 package. 3. Updated AC/DC characteristics for AT89C51SND1C product. 4. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 5. Added note on Flash retention formula for VIH1, in Section "DC Characteristics", page 181.
Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 1 Typical Applications ............................................................................. 2 Block Diagram ....................................................................................... 2 Pin Description ........................................................
AT8xC51SND1C Reset .................................................................................................................. 46 Reset Recommendation to Prevent Flash Corruption ........................................ 47 Idle Mode ............................................................................................................ 47 Power-down Mode.............................................................................................. 48 Registers......................................
Isochronous Transactions....................................................................................92 Miscellaneous ......................................................................................................94 Suspend/Resume Management ..........................................................................95 USB Interrupt System ......................................................................................... 97 Registers........................................................
AT8xC51SND1C Registers............................................................................................................180 Electrical Characteristics ................................................................. 181 Absolute Maximum Rating................................................................................ DC Characteristics............................................................................................ AC Characteristics ..............................................
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