Datasheet

89
AT89C51RB2/RC2
4180D–8051–06/05
Table 67. Default Values
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 68. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 69.
Mnemonic Definition Default value Description
SBV Software Boot Vector FCh
HSB Hardware security Byte 101x 1011b
BSB Boot Status Byte 0FFh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h ATMEL
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: memories F7h AT89C51RB2/RC2 32KB
size and type FBh AT89C51RB2/RC2 16 KB
Copy of the Device ID #3: name and
revision
EFh
AT89C51RB2/RC2 32KB,
Revision 0
FFh
AT89C51RB2/RC2 16 KB,
Revision 0
76543210
------LB1LB0
Bit
Number
Bit
Mnemonic Description
7-
Reserved
Do not clear this bit.
6-
Reserved
Do not clear this bit.
5-
Reserved
Do not clear this bit.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-
Reserved
Do not clear this bit.
1-0 LB1-0
User Memory Lock Bits
see Table 69