Datasheet

AT89C51RB2/RC2

4180D–8051–06/05

Figure 6. Mode Switching Waveforms

The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods

per instruction to 6 clock periods and vice versa. At reset, the speed is set according to

X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the

X2 bit activates the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register

(Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from

standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph-

eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2

mode.

XTAL1:2

XTAL1

CPU Clock

X2 Bit

X2 Modex1 Mode X1 Mode

OSC