Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9 Interrupt Sources with 4 Priority Levels – Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals ISP (In-system Programming) Using Standard VCC Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture – In Standard Mode: 40 MHz (Vcc 2.7V to 5.
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of 1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The Pinout is the standard 40/44 pins of the C52.
AT89C51RB2/RC2 Block Diagram (2) (2) XTAL1 XTAL2 (1) EUART + BRG ALE/ PROG RAM 256x8 C51 CORE PSEN Flash 32Kx8 or 16Kx8 XRAM 1Kx8 Boot ROM 2Kx8 (1) (1) PCA T2 T2EX PCA ECI Vss VCC TxD RxD Figure 1. Block Diagram (1) Timer2 IB-bus CPU EA Notes: Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 (2) (2) Watch Key Dog Board SPI SS MOSI SCK MISO P3 P2 (1) (1) (1) (1) P1 T1 T0 RESET (2) (2) INT Ctrl P0 Timer 0 Timer 1 (2) INT1 WR (2) INT0 RD 1.
SFR Mapping 4 The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) • Power and clock control registers: PCON • Hardware Watchdog T
AT89C51RB2/RC2 Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low Byte DPH 83h Data Pointer High Byte 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Table 3.
Table 6.
AT89C51RB2/RC2 Table 8. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI BRR TBCK RBCK SPD SRC Table 9.
Table 11 shows all SFRs with their address and their reset value. Table 11.
AT89C51RB2/RC2 Pin Configurations 6 36 35 P0.3/AD3 P0.4/AD4 P1.5/CEX2/MISO 7 8 34 33 P0.5/AD5 9 10 5 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.2/AD2 P0.1/AD1 P1.5/CEX2/MISO P1.6/CEX3/SCK 37 P0.0/AD0 3 4 VCC P1.2/ECI P1.3CEX0 P1.4/CEX1 NIC* P0.0/AD0 P1.0/T2 VCC 39 38 P1.1/T2EX/SS 40 2 P1.2/ECI 1 P1.3/CEX0 P1.0/T2 P1.1/T2EX/SS P1.4/CEX1 Figure 2. Pin Configurations 6 5 4 3 2 1 44 43 42 41 40 P1.6/CEX3/SCK 7 8 39 38 P0.4/AD4 P0.6/AD6 P1.7/CEx4/MOSI 9 37 P0.7/AD7 RST P0.
Table 12. Pin Description for 40 - 44 Pin Packages Pin Number Mnemonic DIL LCC VQFP44 1.4 Type Name and Function VSS 20 22 16 I Ground: 0V reference VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0 - P0.7 39 - 32 43 - 36 37 - 30 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs.
AT89C51RB2/RC2 Table 12. Pin Description for 40 - 44 Pin Packages (Continued) Pin Number Mnemonic DIL LCC VQFP44 1.4 P1.0 - P1.7 Type Name and Function I/O CEX4: Capture/Compare External I/O for PCA Module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller.
Table 12. Pin Description for 40 - 44 Pin Packages (Continued) Pin Number Mnemonic DIL LCC PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.
AT89C51RB2/RC2 Port Types AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current.
Oscillator To optimize the power consumption and execution time needed for a specific task, an internal, prescaler feature has been implemented between the oscillator and the CPU and peripherals. Registers Table 13. CKRL Register CKRL – Clock Reload Register (97h) 7 6 5 4 3 2 1 0 CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0 Bit Number Mnemonic 7:0 CKRL Description Clock Reload Register Prescaler value Reset Value = 1111 1111b Not bit addressable Table 14.
AT89C51RB2/RC2 Functional Block Diagram Figure 4.
Enhanced Features X2 Feature In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new features, which are: • X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware Watchdog • SPI interface • 4-level interrupt priority system • power-off flag • ONCE mode • ALE disabling • Some enhanced features are also located in the UART and the timer 2 The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle.
AT89C51RB2/RC2 Figure 6. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit FOSC CPU Clock x1 Mode X2 Mode X1 Mode The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode).
Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 Bit Mnemonic Description Reserved Watchdog Clock 6 WDX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
AT89C51RB2/RC2 Table 16. CKCON1 Register CKCON1 - Clock Control Register (AFh) 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved 0 SPIX2 SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle.
Dual Data Pointer Register (DPTR) The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 17) that allows the program code to switch between them (see Figure 7). Figure 7.
AT89C51RB2/RC2 Table 17. AUXR1 register AUXR1- Auxiliary Register 1(0A2h) 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Bit Number Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 ENBOOT Enable Boot Flash Cleared to disable boot ROM. Set to map the boot ROM between F800h - 0FFFFh. Reserved The value read from this bit is indeterminate.
INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.
AT89C51RB2/RC2 Expanded RAM (XRAM) The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM) space for increased data parameter handling and high-level language usage. AT89C51RB2/RC2 devices have expanded RAM in external data space; maximum size and location are described in Table 18. Table 18. Expanded RAM Address Part Number XRAM Size Start End AT89C51RB2/RC2 1024 00h 3FFh The AT89C51RB2/RC2 has internal data memory that is mapped into four separate segments.
• Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory that is physically located on-chip, logically occupies the first Bytes of external data memory.
AT89C51RB2/RC2 Registers Table 19. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 DPU - M0 - XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description Disable Weak Pull-up 7 DPU Cleared to activate the permanent weak pull up when latch data is logical 1 Set to disactive the weak pull-up (reduce power consumption) 6 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Timer 2 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input.
AT89C51RB2/RC2 Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6 0 1 T2 C/T2 TR2 T2CON T2CON T2EX: (DOWN COUNTING RELOAD VALUE) if DCEN = 1, 1 = UP FFh FFh if DCEN = 1, 0 = DOWN (8-bit) (8-bit) if DCEN = 0, up counting TOGGLE T2CON EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CON RCAP2L (8-bit) TIMER 2 INTERRUPT RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Programmable Clock-out In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator (see Figure 10).
Figure 10.
AT89C51RB2/RC2 Registers Table 20. T2CON Register T2CON – Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 Overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1.
Table 21. T2MOD Register T2MOD – Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51RB2/RC2 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture Modules.
Figure 11. PCA Timer/Counter To PCA Modules FCLK PERIPH/6 FCLK PERIPH/2 CH T0 OVF overflow CL It 16-bit up Counter P1.
AT89C51RB2/RC2 Registers Table 22. CMOD Register CMOD – PCA Counter Mode Register (D9h) 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4.
Table 23. CCON Register CCON – PCA Counter Control Register (D8h) 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description PCA Counter Overflow Flag 7 CF 6 CR Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run Control Bit Must be cleared by software to turn the PCA counter off.
AT89C51RB2/RC2 Figure 12. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt Priority Decoder Module 2 Module 3 Module 4 CMOD. 0 ECF ECCFn CCAPMn. 0 IEN0. 6 EC IEN0. 7 EA PCA Modules: each one of the five compare/capture Modules has six possible functions.
Table 24.
AT89C51RB2/RC2 Table 25. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer/Compare mode.
Table 27.
AT89C51RB2/RC2 PCA Capture Mode To use one of the PCA Modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that Module must be set. The external CEX input for the Module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the Module's capture registers (CCAPnL and CCAPnH).
16-bit Software Timer/ Compare Mode The PCA Modules can be used as software timers by setting both the ECOM and MAT bits in the Modules CCAPMn register. The PCA timer will be compared to the Module's capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 14). Figure 14.
AT89C51RB2/RC2 High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the modules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR must be set (see Figure 15). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. Figure 15.
Pulse Width Modulator Mode All of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the Modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each Module is independently variable using the module's capture register CCAPLn.
AT89C51RB2/RC2 changing the time base for other Modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin.
Serial I/O Port The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3).
AT89C51RB2/RC2 Figure 19. UART Timings in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e. g. 1111 0011b).
AT89C51RB2/RC2 Registers Table 30. SADEN Register SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 31. SADDR Register SADDR - Slave Address Register (A9h) 7 6 5 4 Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 20.
Table 32.
AT89C51RB2/RC2 Table 33. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.
AT89C51RB2/RC2 Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 3 2 1 0 Reset Value = XXXX XXXXb Table 39.
Table 40. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
AT89C51RB2/RC2 Table 41. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage.
Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator.
AT89C51RB2/RC2 Interrupt System The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 22. Figure 22.
Registers A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 43. Priority Level Bit Values IPH. x IPL. x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) If two interrupt requests of different priority levels are received simultaneously, the request of higher-priority level is serviced.
AT89C51RB2/RC2 Table 44. IENO Register IEN0 - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA 6 EC Enable All Interrupt Bit Cleared to disable all interrupts. Set to enable all interrupts. PCA Interrupt Enable Bit Cleared to disable. Set to enable. 5 ET2 Timer 2 Overflow Interrupt Enable Bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt.
Table 45. IPL0 Register IPL0 - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPCL PCA Interrupt Priority Bit see PPCH for priority level. 5 PT2L Timer 2 Overflow Interrupt Priority Bit see PT2H for priority level. 4 PSL Serial Port Priority Bit see PSH for priority level.
AT89C51RB2/RC2 Table 46. IPH0 Register IPH0 - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit.
Table 47. IEN1 Register IEN1 - Interrupt Enable Register (B1h) 7 6 5 4 3 2 1 0 - - - - - ESPI - KBD Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 ESPI SPI Interrupt Enable Bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. 1 - 0 KBD Reserved Keyboard Interrupt Enable Bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt.
AT89C51RB2/RC2 Table 48. IPL1 Register IPL1 - Interrupt Priority Register (B2h) 7 6 5 4 3 2 1 0 - - - - - SPIL - KBDL Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Table 49. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) 7 6 5 4 3 2 1 0 - - - - - SPIH - KBDH Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51RB2/RC2 Interrupt Sources and Vector Addresses Table 50.
Keyboard Interface The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes.
AT89C51RB2/RC2 Registers Table 51. KBF Register KBF - Keyboard Flag Register (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description KBF7 Keyboard Line 7 Flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. Must be cleared by software.
Table 52. KBE Register KBE - Keyboard Input Enable Register (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic Description 7 KBE7 Keyboard Line 7 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard Line 6 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 6 bit in KBF register to generate an interrupt request.
AT89C51RB2/RC2 Table 53. KBLS Register KBLS - Keyboard Level Selector Register (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard Line 7 Level Selection Bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard Line 6 Level Selection Bit Cleared to enable a low level detection on Port line 6.
Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
AT89C51RB2/RC2 drive the network. The Master may select each Slave device by software through port pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions).
Functional Description Figure 26 shows a detailed structure of the SPI Module. Figure 26.
AT89C51RB2/RC2 Figure 27. Full-Duplex Master-Slave Interconnection 8-bit Shift register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU 8-bit Shift register SCK VDD SS VSS Slave MCU Master Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT).
Figure 28. Data Transmission Format (CPHA = 0) 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 29.
AT89C51RB2/RC2 Error Conditions The following flags in the SPSTA signal SPI error conditions: Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated • The SPEN bit in SPCON is cleared.
Figure 31. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS Registers There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs.
AT89C51RB2/RC2 Bit Number Bit Mnemonic SPR1 1 0 SPR0 Description SPR2 SPR1 SPR0 Serial Peripheral Rate 0 0 0 FCLK PERIPH /2 0 0 1 FCLK PERIPH /4 0 1 0 FCLK PERIPH /8 0 1 1 FCLK PERIPH /16 1 0 0 FCLK PERIPH /32 1 0 1 FCLK PERIPH /64 1 1 0 FCLK PERIPH /128 1 1 1 Invalid Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete
Bit Number Bit Mnemonic Description 1 - 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 58) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model.
AT89C51RB2/RC2 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
Table 60. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out Select Bit 2 1 S1 WDT Time-out Select Bit 1 0 S0 WDT Time-out Select Bit 0 Reserved The value read from this bit is undetermined. Do not try to set this bit. S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0Selected Time-out 0(214 - 1) machine cycles, 16.
AT89C51RB2/RC2 ONCE™ Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RB2/RC2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit.
Power Management Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”. Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin.
AT89C51RB2/RC2 Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) VDD Rise Time Oscillator Start-Up Time 1 ms 10 ms 100 ms 5 ms 820 nF 1.2 µF 12 µF 20 ms 2.7 µF 3.9 µF 12 µF Note: These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
Reset Recommendation to Prevent Flash Corruption An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set.
AT89C51RB2/RC2 be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down mode. Figure 34. Power-down Exit Waveform INT0 INT1 XTALA or XTALB Active Phase Power-down Phase Oscillator Restart Phase Active Phase Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs. Exit from Power-down by either reset or external interrupt or keyboard interrupt does not affect the internal RAM content.
Power-off Flag The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated by an exit from Power-down. The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hardware when VCC rises from 0 to its nominal voltage.
AT89C51RB2/RC2 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0.As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches.
Flash EEPROM Memory The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 16K or 32K Bytes of program memory organized in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.
AT89C51RB2/RC2 Flash Registers and Memory Map Hardware Register The AT89C51RB2/RC2 Flash memory uses several registers for its management: • Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. • Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes.
Table 66. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 1 U U U No program lock features enabled. Protection Description 2 P U U MOVC instruction executed from external program memory is disabled from fetching code Bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. ISP and software programming with API are still allowed.
AT89C51RB2/RC2 Table 67.
Table 69. Program Lock Bits of the SSB Program Lock Bits Security level LB0 LB1 1 U U No program lock features enabled. 2 P U ISP programming of the Flash is disabled. 3 X P Same as 2, also verify through ISP programming interface is disabled. Note: Flash Memory Status Protection Description U: unprogrammed or "one" level. P: programmed or "zero" level. X: don’t care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
AT89C51RB2/RC2 Bootloader Architecture Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 36.
Functional Description Figure 37. Bootloader Functional Description Exernal Host with Specific Protocol Communication User Application User Call Management (API ) ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device.
AT89C51RB2/RC2 Bootloader Functionality Introduction The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’s code but can be manually forced into default ISP operation.
Boot Process Figure 39.
AT89C51RB2/RC2 ISP Protocol Description Physical Layer Frame Description The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 1 bit • Flow control: none • Baud rate: autobaud is performed by the bootloader to compute the baud rate choosen by the host. The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 70.
Functional Description Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. • level 1: WRITE_SECURITY (FEh ) For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns ’P’ on write access.
AT89C51RB2/RC2 Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. Checksum Error When a checksum error is detected send ‘X’ followed with CR&LF. Flow Description Overview An initialization step must be performed after each Reset.
Autobaud Performances The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51RB2/RC2 to establish the baud rate.
AT89C51RB2/RC2 Figure 41.
Example Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 00 55 9A BOOTLOADER : 01 0010 00 55 9A . CR LF Programming Atmel function (write SSB to level 2) HOST : 02 0000 03 05 01 F5 BOOTLOADER : 02 0000 03 05 01 F5. CR LF Writing Frame (write BSB to 55h) 100 HOST : 03 0000 03 06 00 55 9F BOOTLOADER : 03 0000 03 06 00 55 9F .
AT89C51RB2/RC2 Blank Check Command Description Figure 43. Blank Check Flow Bootloader Host Blank Check Command Send Blank Check Command Wait Blank Check Command OR Checksum error ’X’ & CR & LF Wait Checksum Error Send Checksum error COMMAND ABORTED Flash blank OR ’.
Display Data Description Figure 44.
AT89C51RB2/RC2 Example Display data from address 0000h to 0020h HOST Read Function : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF (16 data) BOOTLOADER 0010=-----data------ CR LF (16 data) BOOTLOADER 0020=data CR LF ( 1 data) This flow is similar for the following frames: • Reading Frame • EOF Frame/Atmel Frame (only reading Atmel Frame) Description Figure 45.
ISP Commands Summary Table 73. ISP Commands Summary Command Command Name Data[0] Data[1] Command Effect Program Nb Data Byte. 00h Bootloader will accept up to 128 (80h) data Bytes. The data Bytes should be 128 Byte page Flash boundary.
AT89C51RB2/RC2 API Call Description Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h. Results are returned in the registers.
Table 74.
AT89C51RB2/RC2 Electrical Characteristics Absolute Maximum Ratings Note: C = commercial......................................................0°C to 70°C I = industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS (standard voltage) .........-0.5V to + 6.5V Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V Voltage on Any Pin to VSS..........................-0.
TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued) Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5V ± 10% VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3 V IOH = -200 µA VCC - 0.7 V IOH = -3.2 mA VCC - 1.5 V IOH = -7.0 mA 0.9 VCC V VCC = 2.7V to 5.
AT89C51RB2/RC2 DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0to 40 MHz TA = -40°C to +85°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0 to 40 MHz Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage except RST, XTAL1 VIH1 Input High Voltage, RST, XTAL1 Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.45 V IOL = 0.8 mA(4) 0.45 V IOL = 1.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. Figure 46. ICC Test Condition, Active Mode VCC ICC VCC VCC P0 VCC RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 47.
AT89C51RB2/RC2 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low.
Table 76. AC Parameters for a Fix Clock Symbol -M -L Min Max Min Units Max T 25 25 ns TLHLL 35 35 ns TAVLL 5 5 ns TLLAX 5 5 ns TLLIV n 65 65 ns TLLPL 5 5 ns TPLPH 50 50 ns TPLIV 30 TPXIX 30 0 ns 0 ns TPXIZ 10 10 ns TAVIV 80 80 ns TPLAZ 10 10 ns Table 77. AC Parameters for a Variable Clock 112 Symbol Type Standard Clock X2 Clock X Parameter for M Range X Parameter for -L Range Units TLHLL Min 2T-x T-x 15 15 ns TAVLL Min T-x 0.
AT89C51RB2/RC2 External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN PORT 0 TLLAX TAVLL INSTR IN TPLIV TPLAZ A0-A7 TPXIX TPXAV TPXIZ INSTR IN A0-A7 INSTR IN TAVIV PORT 2 External Data Memory Characteristics ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 Table 78.
Table 79.
AT89C51RB2/RC2 Symbol Type Standard Clock X2 Clock X Parameter for M Range X Parameter for L Range Units TRLRH Min 6T-x 3T-x 25 25 ns TWLWH Min 6T-x 3T-x 25 25 ns TRLDV Max 5T-x 2.5 T - x 30 30 ns TRHDX Min x x 0 0 ns TRHDZ Max 2T-x T-x 25 25 ns TLLDV Max 8T-x 4T -x 45 45 ns TAVDV Max 9T-x 4.5 T - x 65 65 ns TLLWL Min 3T-x 1.5 T - x 30 30 ns TLLWL Max 3T+x 1.5 T + x 30 30 ns TAVWL Min 4T-x 2T-x 30 30 ns TQVWX Min T-x 0.
External Data Memory Read Cycle PSEN TLLWL RD TLLAX PORT 0 PORT 2 TWHLH TLLDV ALE TRLRH TRHDZ TAVDV TRHDX A0-A7 TAVWL ADDRESS OR SFR-P2 Serial Port Timing - Shift Register Mode DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 Table 80.
AT89C51RB2/RC2 Shift Register Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA 0 1 2 3 4 5 6 7 TXHDX TXHDV VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI External Clock Drive Waveforms VALID VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCHCX TCLCH TCLCX TCLCL AC Testing Input/Output Waveforms INPUT/OUTPUT VCC -0.5V 0.2 VCC + 0.9 0.2 VCC - 0.1 0.
Figure 50.
AT89C51RB2/RC2 Ordering Information Table 83.
Package Information PDIL40 120 AT89C51RB2/RC2 4180D–8051–06/05
AT89C51RB2/RC2 VQFP44 121 4180D–8051–06/05
PLC44 122 AT89C51RB2/RC2 4180D–8051–06/05
AT89C51RB2/RC2 Datasheet Change Log Changes from 4180A08/02 to 4180B-04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. Changes from 4180B04/03 to 4180C-12/03 1. Max frequency update for 4.5 to 5.5V range up to 60 MHz (internal code execution). Changes from 4180C12/03 - 4180D - 06/05 1. Added Green product ordering information. Page 119. 2. Added note on Flash retention formula for VIH1, in Section “DC Parameters for Standard Voltage”, page 107.
Table of Contents Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ................................
Registers............................................................................................................. 47 Baud Rate Selection for UART for Mode 1 and 3............................................... 47 UART Registers.................................................................................................. 50 Interrupt System ................................................................................. 55 Registers..................................................................
DC Parameters for Standard Voltage ............................................................... 107 DC Parameters for Low Voltage ....................................................................... 109 AC Parameters ................................................................................................. 111 Ordering Information ........................................................................ 119 Package Information ....................................................................
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