Datasheet

3
4266C–CAN–03/08
AT89C51CC03 UART Bootloader
ISP Communication
Management
The purpose of this process is to manage the communication and its protocol between the on-
chip bootloader and an external device (host). The on-chip bootloader implements a Serial pro-
tocol (see Section “Protocol”). This process translates serial communication frames (UART) into
Flash memory accesses (read, write, erase...).
User Call Management Several Application Program Interface (API) calls are available to the application program to
selectively erase and program Flash pages. All calls are made through a common interface (API
calls) included in the bootloader. The purpose of this process is to translate the application
request into internal Flash Memory operations.
Flash Memory
Management
This process manages low level accesses to the Flash memory (performs read and write
accesses).
Bootloader Configuration
Configuration and
Manufacturer
Information
The table below lists Configuration and Manufacturer byte information used by the bootloader.
This information can be accessed through a set of API or ISP commands.
Mapping and Default
Value of Hardware
Security Byte
The 4 MSB of the Hardware Byte can be read/written by software (this area is called Fuse bits).
The 4 LSB can only be read by software and written by hardware in parallel mode (with parallel
programmer devices).
Note: U: Unprogram = 1
P: Program = 0
Mnemonic Description Default value
BSB Boot Status Byte FFh
SBV Software Boot Vector FCh
SSB Software Security Byte FFh
EB Extra Byte FFh
Manufacturer 58h
Id1: Family code D7h
Id2: Product Name FFh
Id3: Product Revision FEh
Bit Position Mnemonic Default Value Description
7 X2B U To start in x1 mode
6 BLJB P
To map the boot area in code area between F800h-
FFFFh
5 reserved U
4 reserved U
3 reserved U
2 LB2 P
To lock the chip (see datasheet)1 LB1 U
0 LB0 U