Datasheet

95
T89C51AC2
4127D–8051–02/03
Table 67. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value = XXXX XX0Xb
bit addressable
76543210
------PADCL -
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1PADCL
ADC Interrupt Priority Level Less Significant Bit
Refer to PSPIH for priority level.
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.