Datasheet

28
T89C51AC2
4127D–8051–02/03
Registers Table 17. PSW Register
PSW (S:D0h)
Program Status Word Register
Reset Value = 0000 0000b
Table 18. AUXR Register
AUXR (S:8Eh)
Auxiliary Register
76543210
CY AC F0 RS1 RS0 OV F1 P
Bit
Number
Bit
Mnemonic Description
7CY
Carry Flag
Carry out from bit 1 of ALU operands.
6AC
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
5F0User Definable Flag 0.
4-3 RS1:0
Register Bank Select Bits
Refer to Table 15 for bits description.
2OV
Overflow Flag
Overflow set by arithmetic operations.
1F1User Definable Flag 1
0P
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
76543210
- - M0 - XRS1 XRS0 EXTRAM A0
Bit
Number
Bit
Mnemonic Description
7-6 -
Reserved
The value read from these bits are indeterminate. Do not set this bit.
5M0
Stretch MOVX control:
the RD/ and the WR/ pulse length is increased according to the value of M0.
M0
Pulse length in clock period
0 6
1 30
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-2 XRS1-0
XRAM size:
Accessible size of the XRAM
XRS
1:0 XRAM size
0 0 256 Bytes
0 1 512 Bytes
1 0 768 Bytes
1 1 1024 Bytes (default)