Datasheet

26
T89C51AC2
4127D–8051–02/03
Figure 14. External Data Read Waveforms
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 15. External Data Write Waveforms
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
ALE
P0
P2
RD 1
DPL or Ri D7:0
DPH or P22
P2
CPU Clock
ALE
P0
P2
WR1
DPL or Ri D7:0
P2
CPU Clock
DPH or P22