Datasheet

110
T89C51AC2
4127D–8051–02/03
Flash Memory Table 82. Timing Symbol Definitions
Table 83. Memory AC Timing
VDD = 5V
± 10%, TA = -40 to +85°C
Figure 54. Flash Memory – ISP Waveforms
Figure 55. Flash Memory – Internal Busy Waveforms
Table 84. AC Parameters for A/D Conversion
Signals Conditions
S (Hardware
condition)
PSEN#,EA L Low
RRST VValid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
T
SVRL
Input PSEN# Valid to RST Edge 50 ns
T
RLSX
Input PSEN# Hold after RST Edge 50 ns
T
BHBL
Flash Internal Busy (Programming) Time 10 ms
Symbol Parameter Min Typ Max Unit
T
SETUP
4µs
ADC Clock Frequency 700 KHz
RST
T
SVRL
PSEN#1
T
RLSX
FBUSY bit
T
BHBL