Datasheet

67
AT89C5132
4173C–USB–07/04
Description The USB device controller provides the hardware that the AT89C5132 need to interface
a USB link to data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Sec-
tion "Clock Controller", page 67. This clock is used to generate a 12 MHz full speed bit
clock from the received USB differential data flow and to transmit data according to full
speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop
(DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-
ing, CRC generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and
the Dual Port RAM, but also the interface with the C51 core itself.
Figure 47 shows how to connect the AT89C5132 to the USB connector. D+ and D- pins
are connected through 2 termination resistors. Value of these resistors is detailed in the
section “DC Characteristics”.
Figure 45. USB Device Controller Block Diagram
Figure 46. USB Connection
Clock Controller The USB controller clock is generated by division of the PLL clock. The division factor is
given by USBCD1:0 Bits in USBCLK register (see Table 70). Figure 47 shows the USB
controller clock generator and its calculation formula. The USB controller clock fre-
quency must always be 48 MHz.
USB
CLOCK
48 MHz 12 MHz
D+
D-
DPLL
SIE
UFI
USB
Buffer
To/From
C51 Cor
e
D+
D-
R
USB
VBUS
R
USB
GND
D+
D-
VSS
To Power Supply