Datasheet

AT89C5132

4173C–USB–07/04

Table 33. Priority Levels

A low-priority interrupt is always interrupted by a higher priority interrupt but not by

another interrupt of lower or equal priority. Higher priority interrupts are serviced before

lower priority interrupts. The response to simultaneous occurrence of equal priority inter-

rupts is determined by an internal hardware polling sequence detailed in Table 34. Thus

within each priority level there is a second priority structure determined by the polling

sequence. The interrupt control system is shown in Figure 19.

Table 34. Priority Within Same Level

IPHxx IPLxx Priority Level

0 0 0 Lowest

011

102

1 1 3 Highest

Interrupt Name Priority Number

Interrupt Address

Vectors

Interrupt Request Flag

Cleared by Hardware

(H) or by Software (S)

INT0

1 (Highest Priority) C:0003h H if edge, S if level

Timer 0 2 C:000Bh H

INT1

3 C:0013h H if edge, S if level

Timer 1 4 C:001Bh H

Serial Port 5 C:0023h S

Reserved 6

Audio Interface 7 C:0033h S

MMC Interface 8 C:003Bh S

Two-wire Controller 9 C:0043h S

SPI Controller 10 C:004Bh S

A-to-D Converter 11 C:0053h S

Keyboard 12 C:005Bh S

Reserved 13 C:0063h -

USB 14 C:006Bh S

Reserved 15 (Lowest Priority) C:0073h -