Datasheet

29
AT89C5132
4173C–USB–07/04
Table 19. Port SFRs
MnemonicAddName 76543210
P0 80h8-bit Port 0 ––––––––
P1 90h8-bit Port 1 ––––––––
P2 A0h8-bit Port 2 –––––––
P3 B0h8-bit Port 3 –––––––
P4 C0h8-bit Port 4 ––––––––
P5 D8h4-bit Port 5 ––––––––
Table 20. Flash Memory SFR
MnemonicAddName 76543210
FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
Table 21. Timer SFRs
MnemonicAddName 76543210
TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
TL0 8Ah Timer/Counter 0 Low Byte –––––––
TH0 8Ch Timer/Counter 0 High Byte –––––––
TL1 8Bh Timer/Counter 1 Low Byte –––––––
TH1 8Dh
Timer/Counter 1 High Byte –––––––
WDTRSTA6hWatchDog Timer Reset ––––––––
WDTPRGA7hWatchDog Timer Program –––––WTO2WTO1WTO0
Table 22. Audio Interface SFRs
MnemonicAddName 76543210
AUDCON0 9Ah Audio Control 0 JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR
AUDCON1 9Bh Audio Control 1 SRC DRQEN MSREQ MUDRN DUP1 DUP0 AUDEN
AUDSTA 9Ch Audio Status SREQ UDRN
AUBUSY
–––––
AUDDAT 9Dh Audio Data AUD7 AUD6 AUD5 AUD4 AUD3 AUD2 AUD1 AUD0
AUDCLK ECh Audio Clock Divider AUCD4 AUCD3 AUCD2 AUCD1 AUCD0