Datasheet

15
AT89C5132
4173C–USB–07/04
Table 3. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
Reset Value = 0000 1000b
Table 4. PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
Reset Value = 0000 0000b
76543210
R1 R0 - - PLLRES - PLLEN PLOCK
Bit
Number
Bit
Mnemonic Description
7 - 6 R1:0
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
5 - 4 -
Reserved
The values read from these Bits are always 0. Do not set these Bits.
3 PLLRES
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
2-
Reserved
The values read from this bit is always 0. Do not set this bit.
1 PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
76543210
R9 R8 R7 R6 R5 R4 R3 R2
Bit
Number
Bit
Mnemonic Description
7 - 0 R9:2
PLL Most Significant Bits R Divider
8 MSB of the 10-bit R divider.