Datasheet

13
AT89C5132
4173C–USB–07/04
Figure 7. PLL Block Diagram and Symbol
Figure 8. PLL Filter Connection
PLL Programming The PLL is programmed using the flow shown in Figure 9. As soon as clock generation
is enabled, the user must wait until the lock indicator is set to ensure the clock output is
stable. The PLL clock frequency will depend on the audio interface clock frequencies.
Figure 9. PLL Programming Flow
PLLEN
PLLCON.1
N6:0
N divider
R divider
VCO
PLLclk
OSCclk R 1+() ×
N1+
-----------------------------------------------=
OSC
CLOCK
PFLD
PLOCK
PLLCON.0
PFILT
CHP
Vref
Up
Down
R9:0
PLL
CLOCK
PLL Clock Symbol
PLL
Cloc
k
V
SS
PFILT
R
C1
C2
V
SS
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?