Datasheet

AT89C5132

4173C–USB–07/04

Figure 6. Mode Switching Waveforms

Note: In order to prevent any incorrect operation while operating in X2 mode, the user must be

aware that all peripherals using clock frequency as time reference (timers…) will have

their time reference divided by two. For example, a free running timer generating an

interrupt every 20 ms will then generate an interrupt every 10 ms.

PLL

PLL Description The AT89C5132’s PLL is used to generate internal high frequency clock (the PLL Clock)

synchronized with an external low-frequency (the Oscillator Clock). The PLL clock pro-

vides the audio interface, and the USB interface clocks. Figure 7 shows the internal

structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

in PLLCON register (see Table 3) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PFILT pin (see

Figure 8). Value of the filter components are detailed in the Section “DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V

ref

pro-

duced by the charge pump. It generates a square wave signal: the PLL clock.

X1 ÷ 2

Clock

X2 Bit

X2 Mode

(1)

STD Mode STD Mode