Datasheet

126
AT89C5132
4173C–USB–07/04
Reset Value = 0001 0100b
Note: 1. When the SPI is disabled, SCK outputs high level.
Table 99. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
Reset Value = 00000 0000b
Table 100. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
Reset Value = XXXX XXXXb
3CPOL
SPI Clock Polarity Bit
(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
2CPHA
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
1 - 0 SPR1:0
SPI Rate Bits 0 and 1
Refer to Table 97 for bit rate description.
76543210
SPIFWCOL-MODF----
Bit
Number
Bit
Mnemonic Description
7SPIF
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
6WCOL
Write Collision Flag
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
5-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
4MODF
Mode Fault
Set by hardware to indicate that the SS
pin is at an appropriate level.
Cleared by hardware to indicate that the SS
pin is at an inappropriate level.
3:0 -
Reserved
The values read from these Bits are indeterminate. Do not set these Bits.
76543210
SPD7SPD6SPD5SPD4SPD3SPD2SPD1SPD0
Bit
Number
Bit
Mnemonic Description
7 - 0 SPD7:0 Synchronous Serial Data
Bit
Number
Bit
Mnemonic Description