Specifications

226
AT85C51SND3Bx
7632A–MP3–03/06
When the AT85C51SND3Bx is the only slave on the bus, it can be useful not to use SS
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
This bit has no effect when CPHA is cleared (see
Section "SS Management",
page 227).
Figure 118. SPI Slave Mode Block Diagram
Note: MSTR bit in SPCON is cleared to select slave mode.
Bit Rate In master mode, the bit rate can be selected from seven predefined bit rates using the
SPR2, SPR1 and SPR0 control bits in SPCON according to
Table 250. These bit rates
are derived from the peripheral clock (F
PER
) issued from the Clock Controller block as
detailed in
Section "Clock Controller", page 27.
In slave mode, the maximum baud rate allowed on the SCK input is limited to FOSC ÷ 4.
Table 250. Serial Bit Rates
Notes: 1. These frequencies are achieved in X1 mode, F
PER
= F
OSC
÷ 2.
2. These frequencies are achieved in X2 mode, F
PER
= F
OSC
.
UARTM
SPSCR.2
8-bit Shift Register
MISO/P3.0
MOSI/P3.1
CPOL
SPCON.3
CPHA
SPCON.2
IQ
CPU or DFC Bus
SPDAT RD
Control
MODF
SPSCR.4
SS/P3.3
SSDIS
SPCON.5
OVR
SPSCR.6
SPIF
SPSCR.7
and
Clock Logic
SPDAT WR
SPTE
SPSCR.3
SCK/P3.2
SPR2 SPR1 SPR0
Bit Rate (kHz) Vs F
PER
(MHz)
F
PER
Divider6
(1)
8
(1)
10
(1)
12
(1)(2)
16
(2)
20
(2)
24
(2)
0 0 0 3000 4000 5000 6000 8000 10000 12000 2
0 0 1 1500 2000 2500 3000 4000 5000 6000 4
0 1 0 750 1000 1250 1500 2000 2500 3000 8
0 1 1 375 500 625 750 1000 1250 1500 16
1 0 0 187.5 250 312.5 375 500 625 750 32
1 0 1 93.75 125 156.25 187.5 250 312.5 375 64
1 1 0 46.875 62.5 78.125 93.75 125 156.25 187.5 128
1 1 1 - - - - - - - Reserved