Features • Audio Processor • • • • • • • • • • • • – Proprietary Digital Signal Processor – MP3 (Full MPEG I/II-Layer 3) Decoder (1) – Windows Media ® Audio (WMA) Decoder (1) – OGG (Vorbis) Decoder (2) – WAV PCM Decoder/Encoder – ADPCM Decoder/Encoder (G726: 40, 32, 24, 16 Kbps) Audio Codec – 16-bit Stereo D/A Converters (3) – Headphone Amplifier with Analog Volume Control(3) – Microphone Pre-Amplifier with Bias Control – 16-bit Mono A/D Converter: Microphone or Line Inputs Recording – Stereo Lines
• Packages – LQFP100, BGA100, Dice Notes: 1. 2. 3. 4. See Ordering Information Future product AT85C51SND3B2 & AT85C51SND3B3 only AT85C51SND3B3 only Description Digital Music Players, Mobile Phones need ready to use low-cost solutions for very fast time to market.
AT85C51SND3Bx Block Diagram Figure 1. AT85C51SND3Bx Block Diagram AT85C51SND3Bx USB Controller HS / FS Device Controller Control Processor Unit Host / OTG Controller Enhanced X2 C51 Core Interrupt Controller Memory Unit LCD Interface Configurable 64 Kbytes Code / Data RAM Clock Controller Oscillator PLL Clock Generator Timer Unit Notes: Memory Controllers Nand Flash SM / xD Cards MMC V4 SD Cards Audio Controller 2 x 16-bit Timers 3V Regulator Watchdog Timer 1.
Application Information The AT85C51SND3Bx allow design of 2 typical applications which differentiate by the power supply voltage: • The Very Low Voltage System The player operates at 1.8V and allows very low power consumption. • The Low Voltage System The player operates at 3V and allows low power consumption. Very Low Voltage 1.8V System Figure 2. Typical Very Low Voltage 1.8V Application AT85C51SND3B3 1.
AT85C51SND3Bx Low Voltage 3V System Figure 3.
Pin Description Pinouts 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P1.4 P1.5 P1.6 P1.7 P2.0/SDINS P2.1/SDLCK P2.2/SDCMD P2.3/SDCLK P2.4/SDDAT0 P2.5/SDDAT1 P2.6/SDDAT2 P2.7/SDDAT3 IOVSS IOVDD NFWP NFCE0 P4.4/NFCE1/SMLCK P4.5/NFCE2/SMINS P4.6/NFCE3/SMCE NFCLE NFALE NFWE NFRE NFD0 NFD1 Figure 4.
AT85C51SND3Bx Signals Description System Table 1. System Signal Description Signal Name RST Type I/O Description Reset Input Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-up resistor (RRST) which allows the device to be reset by connecting a capacitor between this pin and VSS.
Signal Name P4.6:0 Type I/O Alternate Function Description OCLK DCLK DDAT DSEL Port 4 P4 is a 7-bit bidirectional I/O port with internal pull-ups. NFCE1/SMLCK NFCE2/SMINS NFCE3/SMCE LRD/LDE SDR P5.3:0 I/O LCS SCS Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. LA0/LRS SA0 LWR/LRW SWR Table 3.
AT85C51SND3Bx Clock Controller Table 4. Clock Signal Description Signal Name Type Description Alternate Function Input of the on-chip inverting oscillator amplifier X1 I X2 O UPVDD PWR UPVSS GND APVDD PWR APVSS GND To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing.
Signal Name Type Alternate Function NFCLE O NFRE O NFWE O NFCE0 O NFCE0 is active low and is asserted by the nand flash controller each time it makes access to the device 0. NFCE1 O Nand Flash 1 Chip Enable Description Command Latch Enable Signal - Asserted high during command write cycle. Read Enable Signal - Read signal asserted low during NF/SMC read operation. Write Enable Signal - Write signal asserted low during NF/SMC write operation.
AT85C51SND3Bx Signal Name Type UID I Description Alternate Function USB OTG Identifier Input This pin monitors the function of the OTG device. Note: Audio Processor UVCC PWR ULVDD PWR UHVDD PWR UVSS GND UBIAS O P3.7 This input is requested for OTG mode. USB Supply Voltage Connect this pin to USB VBUS power line. USB Pad Low Voltage Connect this pin to LVDD pin. USB Pad High Voltage Connect this pin to HVDD pin.
Signal Name Type Alternate Function Description AVDD2 Analog Power Supply 2 PWR Low Voltage system: connect this pin to LVDD pin. High voltage system: connect this pin to external +3V power supply. AVSS2 GND - Analog Ground 2 Parallel Slave Interface Serial Interfaces - Low Voltage system: connect this pin to LVSS pin. High voltage system: connect this pin to external +3V ground. Table 10.
AT85C51SND3Bx Signal Name Type TXD O RTS O CTS MMI Interface I Description Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Request To Send Hardware Handshake Line Asserted low by hardware when SIO is ready to receive data. Clear To Send Hardware Handshake Line Asserted low by external hardware when SIO is allowed to send data. Alternate Function P3.1 MOSI P3.2 INT0 SCK P3.3 INT1 SS Table 13.
Signal Name Type BVSS GND LVDD PWR Alternate Function Description Battery Ground - Connect this pin to the negative pin of the battery. Low Voltage DC-DC Power Supply output - This pin outputs +1.8V typ. from internal DC-DC (battery powered). Low Voltage Regulator Power Supply Output OCD Interface 14 This pin outputs +1.8V typ. from internal regulator (USB powered or +3V external power supply). Connect this pin to LVDD incase of internal DC-DC usage.
AT85C51SND3Bx Internal Pin Structure Table 17. Detailed Internal Pin Structure Circuit (1) Type Pins Input/Output RST RRST IOVDD N IOVSS 2 osc periods IOVDD Latch Output IOVDD Ps Pm IOVDD Pw Input/Output N P0.7:0 P1.7:0 P2.7:0 P3.5:0 P4.6:0 P5.3:0 OCDT IOVSS 2 osc periods HVDD HVDD HVDD Ps Pm Pw Latch Output Input/Output P3.
Circuit (1) Type Pins SDCLK SCK NFCE3:0 NFCLE NFALE NFWE NFRE NFWP SMCE IOVDD P Output DSEL DDAT DCLK OCLK N IOVSS LWR/LE LA0/LRS LRD/LRW LCS UVCON TXD DPF Input/Output DPF DMF Input/Output DPH DMH Input DCPWR (2) - DCLI(2) DMF DPH DMH RDCP BVDD LVDD P N CVSS 16 AT85C51SND3Bx 7632A–MP3–03/06
AT85C51SND3Bx Circuit (1) Type Pins Output MICBIAS Input MICIN LINR LINL Output OUTR(2) OUTL(2) + AVSS AVSS + Notes: 1. For information on resistor value, input/output levels, and drive capability, refer to Section “DC Characteristics”, page 241. 2. AT85C51SND3B3 only 3.
Power Management The Power Management implements all the internal power circuitry (regulators, links…) as well as power failure detector and reset circuitry. Power Supply The AT85C51SND3B3 embeds the regulators and a DC to DC step-up convertor to be able to operate from either USB power supply (5V nominal) or from a single cell battery such as AAA battery.
AT85C51SND3Bx Schematic Figure 6. Regulator Connection HVDD RLVDD CLV(*) CHV VSS Note: VSS Depending on power supply scheme, CLV may replace CDC capacitor (see Figure 8). Low Voltage DC-DC in AT85C51SND3B3 The low voltage output DC-DC converter supplies power to the internal device and external devices through LVDD power pin. It operates from a single AAA battery. Its nominal voltage output is 1.8V.
Battery Voltage Monitor The battery voltage monitor is a 5-bit / 50 mV resolution A to D converter with fixed conversion range as detailed in Table 18. Table 18. Battery Voltage Value VB4:0 Battery Voltage (V) 00000 [0.9 - 0.95[ 00001 [0.95 - 1.0[ 00010 [1.0 - 1.05[ … Conversion Management … 01110 [1.6 - 1.65[ 01111 [1.65 - 1.7[ 10000 [1.7 - 1.75[ The battery voltage monitor is turned on by setting the VBPEN and VBCEN bits in PCON (see Table 20).
AT85C51SND3Bx Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked (refer to Section “System Clock Generator”, page 29). The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained.
the clocks to the CPU and peripherals. Using INTn input, execution resumes when the input is released (see Figure 10) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 11). This behavior is necessary for decoding the key while it is still pressed. In both cases, execution resumes with the interrupt service routine.
AT85C51SND3Bx Reset In order to secure the product functionality while in power-up or power-down phase or while in running phase, a number of internal mechanisms have been implemented. These mechanisms are listed below and detailed in the following paragraphs. • External RST input • Power Fail Detector (brown-out) • Watchdog timer • Pads control Figure 12 details the internal reset circuitry.
Figure 13.
AT85C51SND3Bx Registers Table 20. PCON Register PCON (0.87h) – Power Control Register 7 6 5 4 3 2 1 0 VBCEN VBPEN DCPBST GF0 DCEN PMLCK PD IDL Bit Number Bit Mnemonic Description Battery Monitor Clock Enable Bit 7 VBCEN 6 VBPEN 5 DCPBST 4 GF0 Set to enable the clock of the battery monitoring. Clear to disable the clock of the battery monitoring. Battery Monitor Power Enable Bit Set to power the battery monitoring. Clear to unpower the battery monitoring.
Bit Number Bit Mnemonic Description High Voltage Detect Flag 6 HVDET 5-3 - Set by hardware when 3V is detected on HVDD pin. Cleared by hardware when 3V is not detected on HVDD pin. Reserved The value of these bits is always 0. Do not set these bits. Watchdog Timer Reset Flag 2 WDTRST 1 EXTRST Set by hardware when the watchdog timer has overflowed triggering and internal reset. Must be cleared by software at power-up.
AT85C51SND3Bx Clock Controller The AT85C51SND3Bx clock controller is based on an on-chip oscillator feeding two onchip Phase Lock Loop (PLL) dedicated for the USB controller (see Section “USB Controller”, page 85) and the Audio Controller (see Section “Audio Controller”, page 149). All internal clocks to the peripherals and CPU core are generated by this controller.
Figure 16. Crystal Connection X1 C1 Q C2 APVSS Clock Generator X2 The clock generator provides the oscillator and higher frequency clocks to the System, the DFC, the memory controllers: Nand Flash and MMC controllers, the USB and the high speed Serial I/O port. It is based on a 480 MHz PLL namely the PLL clock followed by a frequency divider giving a broad range of available clock frequency: the CLOCK GEN clocks. The clock generation is enabled by setting CKGENE bit in CKEN (see Table 32).
AT85C51SND3Bx Figure 18. PLL Block Diagram and Symbol Up N Divider PFLD CHP 480 MHz VCO Down PLLN3:0 PLLCLK.3:0 12 MHz 16 MHz 20 MHz 00 01 10 11 R Divider PLLCKS1:0 PLLR3:0 CKSEL.4:3 PLLCLK.7:4 FREV Primary Divider PLL CLOCK PLL Clock Symbol Table 24. PLL Reverse Clock Selection PLLCKS1:0 PLL Programming Clock Selection (FREV) 00 12 MHz (default) 01 16 MHz 10 20 MHz 11 12 MHz ÷ (PLLR + 1) The PLL is programmed depending on the oscillator clock frequency.
Figure 19. System Clock Generator Block Diagram and Symbols OSC CLOCK 24 MHz 30 MHz 40 MHz CLOCK GEN 00 01 10 11 FSYS Audio Controller Clock ÷2 0 Peripheral Clock 1 SYSCKS1:0 X2 CKSEL.1:0 CKCON.0 CPU Core Clock IDL PCON.0 AUD CLOCK Audio Clock Symbol PER CLOCK Peripheral Clock Symbol CPU CLOCK CPU Core Clock Symbol Table 26.
AT85C51SND3Bx Figure 21. DFC/NFC Clock Generator Block Diagram and Symbol CLOCK GEN OSC 60 MHz 48 MHz 40 MHz 30 MHz 24 MHz 20 MHz 16 MHz 000 001 010 011 100 101 110 111 CKEN.0 DNFCKEN FS DFC Clock NFC Clock DNFC CLOCK DNFCKS2:0 CKSEL.7:5 DFC/NFC Clock Symbol Table 27.
Table 28. MMC Clock Selection MMCCKS2:0 Clock Selection (FS) 000 FOSC (default) 001 60 MHz 010 48 MHz 011 30 MHz 100 24 MHz 101 20 MHz 110 16 MHz 111 FOSC ÷ 2 Table 29.
AT85C51SND3Bx Registers Table 31. CKCON Register CKCON (0.8Fh) – Clock Control Register 7 6 5 4 3 2 1 0 - WDX2 OSCAMP OSCF1 OSCF0 T1X2 T0X2 X2 Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is always 0. Do not set this bit. Watchdog Clock Control Bit 6 WDX2 Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Table 32. CKEN Register CKEN (0.B9h) – Clock Enable Register 7 6 5 4 3 2 1 0 CKGENE PLLEN - PLOCK MMCKEN - SIOCKEN DNFCKEN Bit Number Bit Mnemonic Description Clock Generator Enable Bit 7 CKGENE 6 PLLEN 5 - 4 PLOCK 3 MMCKEN 2 - 1 SIOCKEN 0 DNFCKEN Set to enable the clock generator. Clear to disable the clock generators. PLL Enable Bit Set to enable the 480 MHz PLL. Clear to disable the 480 MHz PLL. Reserved The value read from this bit is always 0. Do not set this bit.
AT85C51SND3Bx Table 33. CKSEL Register CKSEL (0.BAh) – Clock Selection Register 7 6 5 4 3 2 1 0 DNFCKS2 DNFCKS1 DFCCKS0 PLLCKS1 PLLCKS0 SIOCKS SYSCKS1 SYSCKS0 Bit Number Bit Mnemonic Description 7-5 DNFCKS2:0 4-3 PLLCKS1:0 2 SIOCKS 1-0 SYSCKS1:0 DFC/NFC Clock Select Bits Refer to Table 27 for information on selected clock value. PLL Reverse Clock Select Bits Refer to Table 24 for information on selected clock value.
Special Function Registers SFR Pagination The AT85C51SND3Bx implement a SFR pagination mechanism which allows mapping of high number of peripherals in the SFR space. As shown in Figure 24, four pages are accessible through the PPCON (Peripheral Pagination Control) register (see Table 37). The four bits of PPCON: PPS0 to PPS3 are used to select one page as detailed in Table 36. Setting one bit of PPCON using the setb instruction automatically clears the 7 others: e.g.
AT85C51SND3Bx SFR Registers The Special Function Registers (SFRs) of the AT85C51SND3Bx fall into the categories detailed in Table 39 to Table 58. Address is identified as “P.XXh” where P can take the values detailed in Table 38 and XXh is the hexadecimal address from 80h to FFh Table 38. Page Address Notation P Comment Y Register mapped in all pages 3-0 Register mapped in the corresponding page The SFRs mapping within pages is provided together with SFR reset value in Table 58 to Table 58.
Table 42. Interrupt SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 0.A8h Interrupt Enable Control 0 EA EAUP EDFC ES ET1 EX1 ET0 EX0 IEN1 0.B1h Interrupt Enable Control 1 - - EMMC ENFC ESPI EPSI EKB EUSB IPH0 0.B7h Interrupt Priority Control High 0 - IPHAUP IPHDFC IPHS IPHT1 IPHX1 IPHT0 IPHX0 IPL0 0.B8h Interrupt Priority Control Low 0 - IPLAUP IPLDFC IPLS IPLT1 IPLX1 IPLT0 IPLX0 IPH1 0.
AT85C51SND3Bx Table 46. Memory Management SFRs Mnemonic Add Name 7 6 5 4 MEMCBAX 0.F2h Memory CODE Base Address CBAX16:9 MEMDBAX 0.F3h Memory DATA Base Address DBAX16:9 MEMXBAX 0.F4h Memory XDATA Base Address XBAX16:9 MEMCSX 0.F5h Memory CODE Size CSX7:0 MEMXSX 0.F6h Memory XDATA Size XSX7:0 3 2 1 0 3 2 1 0 - - - - 3 2 1 0 DFABTM DFEN Table 47. Scheduler SFRs Mnemonic Add Name 7 SCHCLK - 0.FEh Scheduler Clocks 6 5 4 SCHIDL2:0 SCHGPR3 Y.
Table 49. USB Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 - - - - - - RMWKUP DETACH WAKEUPI USB Device Registers (HOST cleared) UDCON 1.D9h Device Global Control UDINT 1.D8h Device Global Interrupt (bit addressable) - UPRSMI EORSMI EORSTI SOFI MSOFI SUSPI UDIEN 1.DAh Device Global Interrupt Enable - UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE UDADDR 1.DBh Device Address ADDEN UDFNUMH 1.DCh Device Frame Number High - UADD6:0 - - - UDFNUML 1.
AT85C51SND3Bx Table 49. USB Controller SFRs Mnemonic Add Name 7 6 5 4 3 - - - - 2 1 0 USB Pipe Registers (HOST set) UPNUM 1.C9h USB Host Pipe Number - UPRST 1.CAh USB Host Pipe Reset - UPCONX 1.CBh USB Pipe Control - UPCFG0X 1.CCh USB Pipe Configuration 0 UPCFG1X 1.CDh USB Pipe Configuration 1 PNUM2:0 PRST6:0 PFREEZE PTYPE1:0 INMODE AUTOSW RSTDT PNUMS PTOKEN1:0 - PEN PEPNUM3:0 PSIZE2:0 UPCFG2X 1.CFh USB Pipe Configuration 2 DFCRDY PBK1:0 ALLOC - INTFRQ7:0 UPSTAX 1.
Table 50. NFC SFRs Mnemonic Add Name 7 6 5 4 NFBPH 1.94h NF Byte Position (MSB) BP15:8 NFBPL 1.95h NF Byte Position (LSB) BP7:0 3 2 1 0 Table 51. MMC Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 MMCON0 1.B1h MMC Control 0 - DPTRR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS MMCON1 1.B2h MMC Control 1 DATDIR DATEN RXCEN TXCEN MMCON2 1.B3h MMC Control 2 MMBLP 1.B4h MMC Block Length MMSTA 1.B5h MMC Status MMDAT 1.B6h MMC Data MD7:0 MMCMD 1.
AT85C51SND3Bx Table 52. Audio Controller SFRs Mnemonic Add Name Audio Processor Equalizer Band Select 7 6 5 4 3 - - - - 0 2 1 0 APEBS 2.F6h APELEV 2.F7h Audio Processor Equalizer Level - - - ACCON 2.EAh Audio Codec Control - AMBSEL AMBEN AISSEL AIEN AODRV* AOSSEL* AOEN* ACAUX 2.E4h Audio Codec Auxiliary - - - - - - AODIS* AOPRE* ACORG* 2.EBh Audio Codec Right Output Gain - - - AORG4:0* ACOLG* 2.ECh Audio Codec Left Output Gain - - - AOLG4:0* ACIPG 2.
Table 56. Serial I/O Port SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SINT 1.A8h SIO Interrupt - - EOTI OEI PEI FEI TI RI SIEN 1.A9h SIO Interrupt Enable - - EOTIE OEIE PEIE FEIE TIE RIE SBUF 1.AAh SIO Data Buffer SIOD7:0 SBRG0 0.92h SIO Baud Rate Generator 0 CDIV7:0 SBRG1 0.93h SIO Baud Rate Generator 1 BDIV7:0 SBRG2 0.94h SIO Baud Rate Generator 2 ADIV7:0 Table 57. LCD Interface SFRs Mnemonic Add Name LCDCON0 1.
AT85C51SND3Bx Table 59.
Table 60.
AT85C51SND3Bx Table 61.
Table 62.
AT85C51SND3Bx Memory Space The AT85C51SND3Bx provide an “all in one” 64K bytes of RAM split between the three standard C51 memory segments: • CODE • DATA • XDATA To satisfy application needs in term of CODE and XDATA sizes, size and base address of XDATA and CODE segments and base address of DATA segment can be dynamically configured. Figure 25 shows the memory space organization. Figure 25.
Table 63. Register Bank Selection RS1 RS0 Description 0 0 Register bank 0 from 00h to 07h 0 1 Register bank 1 from 08h to 0Fh 1 0 Register bank 2 from 10h to 17h 1 1 Register bank 3 from 18h to 1Fh The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.
AT85C51SND3Bx The Figure 27 shows the memory segments configuration after bootstrap execution along with an example of user memory segments configuration done during firmware start-up. In this figure italicized address are the logical address within segments. Figure 27.
Table 65. MEMCBAX Register MEMCBAX (0.F2h) – Memory Management CODE Base Address Register 7 6 5 4 3 2 1 0 CBAX16 CBAX15 CBAX14 CBAX13 CBAX12 CBAX11 CBAX10 CBAX9 Bit Number Bit Mnemonic Description CODE Base Address Most Significant Bits of Context MEMPID 7-0 CBAX16:9 17-bit CODE Base Address: X XXXX XXX0 0000 0000b. 512-byte alignment, no offset. Reset Value MEMCBA0 = 0 0000 000b Table 66. MEMDBAX Register MEMDBAX (0.
AT85C51SND3Bx Bit Number Bit Mnemonic Description CODE Size Bits of Context MEMPID 7-0 CSX7:0 Size is equals to (CSX+1) x 256 bytes. CODE sizes available: from 256 bytes to 64 Kbytes, by 256-byte steps. Reset Value MEMCSX = 1110 1111b Table 69. MEMXSX Register MEMXSX (0.
AT85C51SND3Bx 7632A–MP3–03/06
AT85C51SND3Bx Interrupt System The AT85C51SND3Bx, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT85C51SND3Bx activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard).
Table 71.
AT85C51SND3Bx Figure 28. Interrupt Control System 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 IEN0.0 00 01 10 11 Timer 0 ET0 IEN0.1 00 01 10 11 External Interrupt 1 EX1 IEN0.2 00 01 10 11 Timer 1 ET1 IEN0.3 00 01 10 11 Serial I/O Port ES IEN0.4 00 01 10 11 Data Flow Controller EDFC IEN0.5 00 01 10 11 Audio Processor EAUP IEN0.6 00 01 10 11 USB Controller EUSB IEN1.0 00 01 10 11 Keyboard EKB IEN1.1 00 01 10 11 PSI Interface EPSI IEN1.
External Interrupts INT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in INT1:0 Input Circuitry. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON register.
AT85C51SND3Bx Registers Table 72. IEN0 Register IEN0 (0.A8h) – Interrupt Enable Register 0 7 6 5 4 3 2 1 0 EA EAUP EDFC ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description Enable All Interrupt Bit 7 EA Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit.
Table 73. IEN1 Register IEN1 (0.B1h) – Interrupt Enable Register 1 7 6 5 4 3 2 1 0 - - EMMC ENFC ESPI EPSI EKB EUSB Bit Number Bit Mnemonic Description 7-6 - 5 EMMC 4 ENFC 3 ESPI 2 EPSI 1 EKB 0 EUSB Reserved The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Enable Bit Set to enable MMC/SD interrupt. Clear to disable MMC/SD interrupt. NFC Interrupt Enable Bit Set to enable IDE interrupt. Clear to disable IDE interrupt.
AT85C51SND3Bx Table 74. IPH0 Register IPH0 (0.B7h) – Interrupt Priority High Register 0 7 6 5 4 3 2 1 0 - IPHAUP IPHDFC IPHS IPHT1 IPHX1 IPHT0 IPHX0 Bit Number Bit Mnemonic Description 7 - 6 IPHAUP 5 IPHDFC 4 IPHS 3 IPHT1 2 IPHX1 1 IPHT0 0 IPHX0 Reserved The value read from this bit is indeterminate. Do not set this bit. AUP Interrupt Priority Level Msb Refer to Table 70 for priority level description.
Table 75. IPH1 Register IPH1 (0.B3h) – Interrupt Priority High Register 1 7 6 5 4 3 2 1 0 - - IPHMMC IPHNFC IPHSPI IPHSPI IPHKB IPHUSB Bit Number Bit Mnemonic Description 7-6 - 5 IPHMMC 4 IPHNFC 3 IPHSPI 2 IPHPSI 1 IPHKB 0 IPHUSB Reserved The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Priority Level Msb Refer to Table 70 for priority level description. NFC Interrupt Priority Level Msb Refer to Table 70 for priority level description.
AT85C51SND3Bx Table 76. IPL0 Register IPL0 (0.B8h) - Interrupt Priority Low Register 0 7 6 5 4 3 2 1 0 - IPLAUP IPLDFC IPLS IPLT1 IPLX1 IPLT0 IPLX0 Bit Number Bit Mnemonic Description 7 - 6 IPLAUP 5 IPLDFC 4 IPLS 3 IPLT1 2 IPLX1 1 IPLT0 0 IPLX0 Reserved The value read from this bit is indeterminate. Do not set this bit. AUP Interrupt Priority Level Lsb Refer to Table 70 for priority level description.
Table 77. IPL1 Register IPL1 (0.B2h) – Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - - IPLMMC IPLNFC IPLSPI IPLPSI IPLKB IPLUSB Bit Number Bit Mnemonic Description 7-6 - 5 IPLMMC 4 IPLNFC 3 IPLSPI 2 IPLPSI 1 IPLKB 0 IPLUSB Reserved The value read from these bits is always 0. Do not set these bits. MMC/SD Interrupt Priority Level Lsb Refer to Table 70 for priority level description. NFC Interrupt Priority Level Lsb Refer to Table 70 for priority level description.
AT85C51SND3Bx Timers/Counters The AT85C51SND3Bx implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
Figure 31. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK 0 Timer 0 Clock 1 OSC CLOCK PER CLOCK ÷2 T0X2 T1X2 CKCON.1 CKCON.2 TIM0 CLOCK TIM1 CLOCK Timer 0 Clock Symbol Timer 0 Timer 1 Clock 1 OSC CLOCK ÷2 0 Timer 1 Clock Symbol Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 32, Figure 34, Figure 36, and Figure 38 show the logical configuration of each mode.
AT85C51SND3Bx Figure 32. Timer/Counter x (x = 0 or 1) in Mode 0 TIMx CLOCK ÷6 0 THx (8 bits) 1 TLx Overflow (5 bits) Tx TFx TCON Reg Timer x Interrupt Request C/Tx# TMOD Reg INTx GATEx TMOD Reg TRx TCON Reg Figure 33. Mode 0 Overflow Period Formula TFxPER= Mode 1 (16-bit Timer) 6 ⋅ (16384 – (THx, TLx)) FTIMx Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 34). The selected input increments TL0 register.
Figure 36. Timer/Counter x (x = 0 or 1) in Mode 2 TIMx CLOCK ÷6 0 Overflow TLx (8 bits) 1 TFx TCON reg Tx Timer x Interrupt Request C/Tx# TMOD Reg INTx GATEx THx (8 bits) TMOD Reg TRx TCON Reg Figure 37. Mode 2 Auto-reload Period Formula TFxPER= Mode 3 (2 x 8-bit Timers) 6 ⋅ (256 – THx) FTIMx Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 38). This mode is provided for applications requiring an additional 8bit Timer or Counter.
AT85C51SND3Bx Timer 0 Enhanced Mode Timer 0 overflow period can be increased in all modes by enabling a divider as detailed in Figure 40. This mode is implemented to allow higher time periods as it can be used for example as a scheduler time base with auto-reload (mode 2). Timer 0 enhanced mode is enabled by programming T0ETB2:0 bits in SCHCLK (see Table 87) to a value other than 000b and according to Table 79. Figure 40. Timer/Counter 0 Enhanced Mode ÷ 2N Timer 0 Overflow TF0 TCON.
• It is important to stop the Timer/Counter before changing modes. Table 80. Timer/counter 1 Operating Modes M11 M01 Mode Operation 0 0 0 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 1 16-bit Timer/Counter. 1 0 2 8-bit auto-reload Timer/Counter (TL1). 1 1 3 Timer/Counter halted. Retains count.
AT85C51SND3Bx Registers Table 81. TCON Register TCON (0.88h) – Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description Timer 1 Overflow Flag 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control Bit Clear to turn off Timer/Counter 1.
Table 82. TMOD Register TMOD (0.89h) – Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 6 C/T1# 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
AT85C51SND3Bx Table 84. TL0 Register TL0 (0.8Ah) – Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 85. TH1 Register TH1 (0.8Dh) – Timer 1 High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 High Byte of Timer 1 Reset Value = 0000 0000b Table 86. TL1 Register TL1 (0.
Table 87. SCHCLK Register SCHCLK (0.FEh) – Scheduler Clocks Register 7 6 5 4 3 2 1 0 - T0ETB2 T0ETB1 T0ETB0 - - - - Bit Number Bit Mnemonic Description 7 - 6-4 T0ETB2:0 3-0 - Reserved The value read from this bit is always 0. Do not set this bit. Timer 0 Enhanced Time Base Bits Refer to Table 79 for dividing values. Reserved The value read from these bits is always 0. Do not set these bits.
AT85C51SND3Bx Watchdog Timer The AT85C51SND3Bx implement a hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 42, the 14-bit prescaler is fed by the WDT clock detailed in Section “Clock Controller”.
Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset. This overflow generates a low level 96 oscillator periods pulse on the RST pin to globally reset the application (refer to Section “Watchdog Timer Reset”, page 24).
AT85C51SND3Bx Registers Table 89. WDTRST Register WDTRST (0.A6h Write only) – Watchdog Timer Reset Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - Watchdog Control Value Reset Value = XXXX XXXXb Table 90. WDTPRG Register WDTPRG (0.A7h) – Watchdog Timer Program Register 7 6 5 4 3 2 1 0 - - - - - WTO2 WTO1 WTO0 Bit Number Bit Mnemonic Description 7-3 - 2-0 WTO2:0 Reserved The value read from these bits is indeterminate.
Data Flow Controller The Data Flow Controller (DFC) embedded in the AT85C51SND3Bx is the multimedia data transfer manager. Up to two data transfers can be established through two physical data channels between a source peripheral and a destination peripheral. Figure 45 shows which peripherals are connected to the internal bus which are: the CPU internal bus, the multimedia data bus and the DFC control bus. Figure 45. DFC Internal Architecture RAM CPU USB AUP DFC PSI SPI DFC CLOCK SIO DFEN DFCON.
AT85C51SND3Bx Table 92 shows the different peripherals (source or destination) ID number. These numbers are used to program the SID and the DID in the DFD. Table 91. Data Flow Descriptor Content Byte Number Byte Mnemonic Description 0 SID 1 DID Source Identifier See Table 92 for peripheral ID number. Destination Identifier See Table 92 for peripheral ID number. Data Packet Size Decimal value giving the packet size as 2 DPS. DPS takes value from 0 (1-byte packet size) to 13 (8192-byte packet size).
selected as source, the null device is always ready and sends the data (2 bytes) of the initialized CRC value MSB first. Channel Priority The Data Flow Controller bandwidth is shared between Channel 0 and Channel 1. In case both channels are ready to transfer data, bus bandwidth is shared on a byte by byte basis. In order to allocate maximum bandwidth to a specified channel, priority can be assigned to channel 0 or to channel 1 by setting the DFPRIO1:0 bits in DFCON according to Table 93.
AT85C51SND3Bx Figure 46. Immediate Data Flow Abort Diagram Data bus DP DFABTx DFBSYx Remaining DP N+2 N+1 N Figure 47. Delayed Data Flow Abort Diagram Data bus DP DP N+1 N DFABTx DFBSYx Remaining DP N+2 Data Flow Configuration Prior to any operation, the DFC must be configured in term of clock source and channel priority, then DFC can be enabled. Each time a data flow must be established, a data flow descriptor must be written to the DFC.
Registers Table 94. DFCON Register DFCON (1.89h) – DFC Control Register 7 6 5 4 3 2 1 0 - DFRES - DFCRCEN DFPRIO1 DFPRIO0 DFABTM DFEN Bit Number Bit Mnemonic Description 5 - 6 DFRES 5 - 4 Reserved The value read from this bit is always 0. Do not set this bit. Data Flow Controller Reset Bit Set then clear this bit to reset the Data Flow Controller by software. Reserved The value read from this bit is always 0. Do not set this bit.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Channel 0 Destination Ready Flag 3 DRDY0 2 SRDY0 1 EOFI0 0 DFBSY0 Set by hardware when the source peripheral of channel 0 is ready. Cleared by hardware when the source peripheral of channel 0 is not ready. Channel 0 Source Ready Flag Set by hardware when the destination peripheral of channel 0 is ready. Cleared by hardware when the destination peripheral of channel 0 is not ready.
Table 97. DFD0 Register DFD0 (1.8Ah) – DFC Channel 0 Data Flow Descriptor Register 7 6 5 4 3 2 1 0 DFD0D7 DFD0D6 DFD0D5 DFD0D4 DFD0D3 DFD0D2 DFD0D1 DFD0D0 Bit Number Bit Mnemonic Description Channel 0 Data Flow Descriptor Data 7-0 DFD0D7:0 Write data flow descriptor to this register as detailed in Table 91. Read to get the remaining number of data packet after a delayed abort. MSB is read first. Reset Value = 0000 0000b Table 98. DFD1 Register DFD1 (1.
AT85C51SND3Bx USB Controller The AT85C51SND3Bx Implements a USB controller allowing the AT85C51SND3Bx to act as a USB device or a USB host. The main features of the USB controller: Description • Full-speed and high-speed device. • Full-speed host with OTG compliance. • Automatic Data Flow Controller (DFC) transfer without CPU support. • 2368 bytes of DPRAM.
Figure 50. USB Connection UBIAS RUB UVCON ON UVCC Out CUB OTG 5V Generator RUFT DPF RUFT D+ DMF D- UVSS DPH UID ID VBUS DMH GND VSS General Operating Modes Introduction After a hardware reset, the USB controller is disabled. When enabled, the USB controller has to run the Device Controller or the Host Controller. This is performed using the ID detection.
AT85C51SND3Bx • The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not cleared. • The SPDCONF bits can be set by software. After setting USBE, the USB Controller enters in the Host or in the Device state (according to the UID pin level). The selected controller is ‘Idle’. The USB Controller can at any time be ‘stopped’ by clearing USBE. In fact, clearing USBE acts as an hardware reset.
There are 2 kinds of interrupts: processing (i.e. their generation are part of the normal processing) and exception (errors).
AT85C51SND3Bx Speed Control Device Mode When the USB interface is configured in device mode, the speed selection (Full Speed or High Speed) is performed automatically by the USB controller during the USB Reset. A the end of the USB reset, the USB controller automatically enables or disables highspeed terminations and pull-up. Note: It is possible to force the speed of the protocol, through the SPDCONF1:0 bits. For normal operations, SPDCONF1:0 must be cleared. For all other operations (e.g.
When using this mode, there is no influence over the USB controller. Unused [DPADDH – DPADDL] Endpoint 1 to N Endpoint 0 USB DPRAM Memory Management The controller only supports the following memory allocation management: The reservation of a Pipe or an Endpoint can only be made in the growing order (Pipe/Endpoint 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order. The reservation of a Pipe or an Endpoint “ki” is done when its ALLOC bit is set.
AT85C51SND3Bx • First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory of each is reserved in the DPRAM. • Then, the Pipe/Endpoint 3 is disabled (EPEN=0), but its memory reservation is internally kept by the controller. • Its ALLOC bit is cleared: the Pipe/Endpoint 4 “slides” down, but the Pipe/Endpoint 5 does not “slide”. • Finally, if the firmware chooses to reconfigure the Pipe/Endpoint 3, with a bigger size.
OTG Timers Customizing It is possible to refine some OTG timers thanks to the OTGTCON register (see Table 108). This register is multiplexed with the OTGCON register. The timers are as defined in the OTG specification: • AWaitVrise time-out. [OTG] chapter 6.6.5.1 • VbBusPulsing. [OTG] chapter 5.3.4 • PdTmOutCnt. [OTG] chapter 5.3.2 • SRPDetTmOut. [OTG] chapter 5.3.3 Table 101. OTG Timer Configuration PAGE1:0 VALUE2:0 Timing Parameter 00 AWaitVrise time-out = 20 ms.
AT85C51SND3Bx The control logic of the UVCC pad outputs 2 signals: • The “session_valid” signal is active high when the voltage on the UVCC pin is higher or equal to 1.4V. • The “Va_Vbus_valid” signal is active high when the voltage on the UVCC pin is higher or equal to 4.4V. In the Host mode, the VBUS flag follows the next hysteresis rule: • VBUS is set when the voltage on the UVCC pin is higher or equal to 4.4 V. • VBUS is cleared when the voltage on the UVCC pin is lower than 1.4 V.
ID Detection The ID pin transition is detected thanks to the following architecture: Figure 58. ID Detection Input Block Diagram RPU VDD Internal Pull Up UID ID IDTI USBSTA.1 USBINT.1 By default, (no A-plug or B-plug), the macro is in the Peripheral mode (internal pull-up). The IDTI interrupt is triggered when a A-plug (Host) is plugged or unplugged. The interrupt is not triggered when a B-plug (Peripheral) is plugged or unplugged.
AT85C51SND3Bx Bit Number Bit Mnemonic Description VBUS Transition Interrupt Enable Bit 0 VBUSTE Set this bit to enable the VBUS Transition interrupt generation. Clear this bit to disable the VBUS Transition interrupt generation. Reset Value = 0010 0000b Table 103. USBSTA Register USBSTA (1.E2h) – USB General Status Register 7 6 5 4 3 2 1 0 - - - - - SPEED ID VBUS Bit Number Bit Mnemonic Description 7-3 - 2 SPEED 1 ID 0 VBUS Reserved The value read from these bits is always 0.
Table 105. UDPADDH Register UDPADDH (1.E4h) – USB Dual Port Ram Direct Access High Register 7 6 5 4 3 DPACC - - - - Bit Number 2 1 0 DPADD10:8 Bit Mnemonic Description DPRAM Direct Access Bit 7 DPACC 6-3 - 2-0 Set this bit to directly read the content the Dual-Port RAM (DPR) data through the UEDATX or UPDATX registers. See Section “Memory Access Capability” for more details. Clear this bit for normal operation and access the DPR through the endpoint FIFO.
AT85C51SND3Bx Bit Number Bit Mnemonic Description HNP Request Bit 5 HNPREQ 4 SRPREQ 3 SRPSEL Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP when the controller is in the Host mode (A). Cleared by hardware after the HNP completion. SRP Request Bit Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the controller is initiating a SRP. SRP Selection Bit 2 Set to choose VBUS pulsing as SRP method.
Table 109. OTGIEN Register OTGIEN (1.E7h) – USB OTG Interrupt Enable Register 7 6 5 4 3 2 1 0 - - STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE Bit Number Bit Mnemonic Description 7-6 - 5 STOE Reserved The value read from these bits is always 0. Do not set these bits. Suspend Time-out Error Interrupt Enable Bit Set to enable the STOI interrupt. Clear to disable the STOI interrupt. 4 HNP Error Interrupt Enable Bit HNPERRE Set to enable the HNPERRI interrupt.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Role Exchange Interrupt Flag 3 ROLEEXI 2 BCERRI 1 VBERRI Set by hardware when the USB controller has successfully swapped its mode, due to an HNP negotiation: Host to Device or Device to Host. Shall be cleared by software. See for more details. B-Connection Error Interrupt Flag Set by hardware when an error occur during the B-Connection. Shall be cleared by software. V-Bus Error Interrupt Flag Set by hardware when a drop on VBus has been detected.
USB Software Operating modes Depending on the USB operating mode, the software should perform some of the following operations: Power On the USB interface • Power-On USB pads regulator • Wait USB pads regulator ready state • Configure PLL interface • Enable PLL • Check PLL lock • Enable USB interface • Configure USB interface (USB speed, Endpoints configuration...
AT85C51SND3Bx USB Device Operating modes Introduction The USB device controller supports high speed and full speed data transfers. In addition to the default control endpoint, it provides six other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • Endpoint 0: programmable size FIFO up to 64 bytes, default control endpoint. • Endpoints 1 and 2: programmable size FIFO up to 512 bytes in ping-pong mode.
At the end of the reset process (Full or High), the end of reset interrupt (EORSTI) is generated. Then the CPU should read the SPEED bit to know the speed mode of the device. Note that the USB device controller starts in the Full-speed mode after power on. Endpoint Reset An endpoint can be reset at any time by setting in the UERST register the bit corresponding to the endpoint (EPRSTx).
AT85C51SND3Bx Endpoint Activation – Clear DFCRDY to freeze the DFC transfer, – If the CPU EPNUM has to be changed: EPNUMS cleared, EPNUM = endpoint0 – Read endpoint 0 data (UEDATX) – Set DFCRDY. This resumes the DFC transfer. The endpoint is maintained under reset as long as the EPEN bit is not set. The following flow must be respected in order to activate an endpoint: Figure 60.
• the host sends a SETUP command (SET_ADDRESS(addr)), • the firmware records that address in UADD, but keep ADDEN cleared, • the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet), • then, the firmware can enable the USB device address by setting ADDEN. The only accepted address by the controller is the one stored in UADD. ADDEN and UADD shall not be written at the same time. UADD contains the default address 00h after a power-up or USB reset.
AT85C51SND3Bx Figure 61. Detach a device in Full-speed: UVREF UVREF D+ D+ D- D- EN=1 Remote Wake-Up STALL Request Detach, then Attach EN=1 The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent by the device on its own initiative. Anyway, to do that, the device should first have received a DEVICE_REMOTE_WAKEUP request from the host.
This function is compliant with the Chapter 8 test from PMTC that send extra status for a GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the status. All extra status will be automatically STALL’ed until the next SETUP request. STALL Handshake and Retry Mechanism The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ request bit is set and if there is no retry required. CONTROL Endpoint Management A SETUP request is always ACK’ed.
AT85C51SND3Bx Control Read The next figure shows a control read transaction. The USB controller has to manage the simultaneous write requests from the CPU and the USB host: SETUP USB line RXSTPI DATA SETUP IN STATUS IN OUT NAK HW SW RXOUTI TXINI OUT HW SW HW SW SW Wr Enable HOST Wr Enable CPU A NAK handshake is always generated at the first status stage command. When the controller detect the status stage, all the data written by the CPU are erased, and clearing TXINI has no effects.
banks, clearing the FIFOCON bit will switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accordance with the status of the new bank. RXOUTI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty.
AT85C51SND3Bx • The CPU can read the data from the current bank (“N” read of UEDATX), • The CPU can free the bank by clearing FIFOCON when all the data is read, that is: – after “N” read of UEDATX, – as soon as RWAL is cleared by hardware. If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already ready and RXOUTI is set immediately.
writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON bits are automatically updated by hardware regarding the status of the next bank. TXINI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can write data to the bank, and cleared by hardware when the bank is full.
AT85C51SND3Bx • The CPU can free the bank by clearing FIFOCON when all the data are written, that is: – after “N” write into UEDATX – as soon as RWAL is cleared by hardware. If the endpoint uses 2 banks, the second one can be read by the HOST while the current is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already ready (free) and TXINI is set immediately.
Table 111. Abort flow Endpoint Abort Clear UEIENX. TXINE NBUSYBK =0 Yes Disable the TXINI interrupt. Abort is based on the fact that no banks are busy, meaning that nothing has to be sent. No Endpoint reset Yes KILLBK=1 Kill the last written bank. KILLBK=1 Wait for the end of the procedure. No Abort done Isochronous Mode For Isochronous IN endpoints, it is possible to automatically switch the banks on each start of frame (SOF). This is done by setting ISOSW.
AT85C51SND3Bx Interrupts Figure 62 shows all the device interrupts sources while Figure 63 details the endpoint interrupt sources. Figure 62. USB Device Controller Interrupt System UPRSMI UDINT.6 UPRSME UDIEN.6 EORSMI UDINT.5 EORSME UDIEN.5 WAKEUPI UDINT.4 WAKEUPE UDIEN.4 EORSTI UDINT.3 EORSTE USB Device Interrupt UDIEN.3 SOFI UDINT.2 SOFE UDIEN.2 MSOFI UDINT.1 MSOFE UDIEN.1 SUSPI UDINT.0 SUSPE UDIEN.0 There are 2 kinds of interrupts: processing (i.e.
Figure 63. USB Device Controller Endpoint Interrupt System Endpoint n (n= 0-6) OVERFI UESTA0X.6 UNDERFI UESTA0X.5 FLERRE UEIENX.7 NAKINI UEINTX.6 NAKINE UEIENX.6 NAKOUTI UEINTX.4 NAKOUTE EPINTn UEIENX.4 UEINT.n Endpoints Interrupt RXSTPI UEINTX.3 RXSTPE UEIENX.3 RXOUTI UEINTX.2 RXOUTE UEIENX.2 STALLI UEINTX.1 STALLE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
AT85C51SND3Bx Registers USB Device General Registers Table 112. UDCON Register UDCON (1.D9h) – USB Device General Control Register 7 6 5 4 3 2 1 0 - - - - - - RMWKUP DETACH Bit Number 7-2 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Remote Wake-up Bit 1 RMWKUP 0 DETACH Set to send an “upstream-resume” to the host for a remote wake-up. Cleared by hardware. Clearing by software has no effect.
Bit Number Bit Mnemonic Description End Of Reset Interrupt Flag 3 EORSTI 2 SOFI 1 MSOFI Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers an USB interrupt if EORSTE is set. Shall be cleared by software. Setting by software has no effect. Start Of Frame Interrupt Flag Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms). This triggers an USB interrupt if SOFE is set.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Suspend Interrupt Enable Bit 0 SUSPE Set to enable the SUSPI interrupt. Clear to disable the SUSPI interrupt. Reset Value = 0000 0000b Table 115. UDADDR Register UDADDR (1.DBh) – USB Device Address Register 7 6 5 4 3 2 1 0 ADDEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic Description Address Enable Bit 7 ADDEN 6-0 UADD6:0 Set to activate the UADD (USB address). Cleared by hardware.
Bit Number Bit Mnemonic Description Frame Number Lower Flag 7-0 FNUM7:0 Set by hardware. These bits are the 8 LSB of the 11-bits Frame Number information. Reset Value = 0000 0000b Table 118. UDMFN Register UDMFN (1.DEh) – USB Device Frame Number Register 7 6 5 4 3 2 1 0 - - - FNCERR - - - - Bit Number 7-5 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits.
AT85C51SND3Bx Bit Number 7 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Endpoint FIFO Reset Bits 6-0 EPRST6:0 Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. See Section “Endpoint Reset” for more information. Then, cleared by software to complete the reset operation and start using the FIFO. Reset Value = 0000 0000b Table 121. UECONX Register UECONX (1.
Table 122. UECFG0X Register UECFG0X (1.CCh) – USB Endpoint Configuration 1 Register 7 6 EPTYPE1:0 Bit Number 5 4 3 2 1 0 - - ISOSW AUTOSW NYETDIS EPDIR Bit Mnemonic Description Endpoint Type Bits 7-6 EPTYPE1:0 5-4 - Set this bit according to the endpoint configuration: 00b: Control10b: Bulk 01b: Isochronous11b: Interrupt Reserved The value read from these bits is always 0. Do not set these bits. Isochronous Switch Bit 3 ISOSW Set to automatically switch banks on each SOF.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Endpoint Bank Bits 3-2 EPBK1:0 Set this field according to the endpoint size: 00b: Single bank 01b: Double bank 1xb: Reserved. Do not use this configuration. Endpoint Allocation Bit 1 ALLOC 0 - Set this bit to allocate the endpoint memory. Clear to free the endpoint memory. See Section “Endpoint Activation” for more details. Reserved The value read from these bits is always 0. Do not set these bits. Reset Value = 0000 0000b Table 124.
Bit Number Bit Mnemonic Description Busy Bank Flag 1-0 Set by hardware to indicate the number of busy bank. For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer. NBUSYBK1: For OUT endpoint, it indicates the number of busy bank(s) filled by OUT 0 transaction from the host. 00b: All banks are free 01b: 1 busy bank 10b: 2 busy banks 11b: Reserved. Reset Value = 0000 0000b Table 125. UESTA1X Register UESTA1X (1.
AT85C51SND3Bx Table 126. UEINTX Register (bit addressable) UEINTX (1.C8h) – USB Endpoint Interrupt Register 7 6 5 4 3 2 1 0 FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLI TXINI Bit Number Bit Mnemonic Description FIFO Control Bit 7 FIFOCON For OUT and SETUP Endpoint: Set by hardware when a new OUT message is stored in the current bank, at the same time than RXOUT or RXSTP. Clear to free the current bank and to switch to the following bank. Setting by software has no effect.
Bit Number Bit Mnemonic Description Stall Interrupt Flag 1 STALLI Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been detected in a OUT isochronous endpoint. Shall be cleared by software. Setting by software has no effect. Transmitter Ready Interrupt Flag 0 TXINI Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is triggered (if enabled). Shall be cleared by software to handshake the interrupt.
AT85C51SND3Bx Table 128. UEDATX Register UEDATX (1.D3h) – USB Endpoint Data Register 7 6 5 4 3 2 1 0 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 Bit Number Bit Mnemonic Description Data Bits 7-0 DAT7:0 Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM. Reset Value = 0000 0000b Table 129. UEBCHX Register UEBCHX (1.
Table 131. UEINT Register UEINT (1.D6h) – USB Endpoint Interrupt Register 7 6 5 4 3 2 1 0 - EPINT6 EPINT5 EPINT4 EPINT3 EPINT2 EPINT1 EPINT0 Bit Number 7 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Endpoint Interrupts Bits 6-0 EPINT6:0 Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding endpoint interrupt enable bit is set. Cleared by hardware when the interrupt source is served.
AT85C51SND3Bx USB Host Operating Modes Pipe Description For the USB Host controller, the term of Pipe is used instead of Endpoint for the USB Device controller (see Figure 64). A Host Pipe corresponds to a Device Endpoint, as described in the USB specification. Figure 64. Pipes and Endpoints in a USB system In the USB host controller, a Pipe will be associated to a Device Endpoint, considering the Device Configuration Descriptors. Detach The reset value of the DETACH bit is 1.
The Host controller enters in Suspend state when the USB bus is in Suspend state, i.e. when the Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is minimum. The Host controller exits to the Suspend state when starting to generate the SOF over the USB line. Device Detection A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In other words, when the USB Host Controller detects the Device pull-up on the D+ line.
AT85C51SND3Bx Pipe Configuration The following flow must be respected in order to activate a Pipe: Figure 66.
USB Reset The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has been set. When a USB Reset has been sent, all the Pipe configuration and the memory allocation are reset. The General Host interrupt enable register is left unchanged.
AT85C51SND3Bx The firmware has to change the Token for each phase. The initial data toggle is set for the corresponding token (ONLY for Control Pipe): OUT Pipe Management • SETUP: Data0 • OUT: Data1 • IN: Data1 (expected data toggle) The Pipe must be configured and not frozen first. Note: if the firmware decides to switch to suspend mode (clear SOFE) even if a bank is ready to be sent, the USB controller will automatically exit from Suspend mode and the bank will be sent.
“Manual” Mode The TXOUT bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the next bank.
AT85C51SND3Bx “Autoswitch” Mode In this mode, the clear of the FIFOCON bit is performed automatically by hardware each time the Pipe bank is full. The firmware has to check if the next bank is empty or not before writing the next data. On TXOUT interrupt, the firmware fills a complete bank. A new interrupt will be generated each time the current bank becomes free. IN Pipe management The Pipe must be configured first.
“Autoswitch” Mode In this mode, the clear of the FIFOCON bit is performed automatically by hardware each time the Pipe bank is empty. The firmware has to check if the next bank is empty or not before reading the next data. On RXIN interrupt, the firmware reads a complete bank. A new interrupt will be generated each time the current bank contains data to read. The acknowledge of the RXIN interrupt is always performed by software.
AT85C51SND3Bx Figure 68. USB Host Controller Pipe Interrupt System Pipe n (n= 0-6) OVERFI UPSTAX.6 UNDERFI UEPSTAX.5 FLERRE UPIENX.7 NAKEDI UPINTX.6 NAKEDE UPIENX.6 PERRI UPINTX.4 PERRE PINTn UPIENX.4 UPINT.n Pipes Interrupt TXSTPI UPINTX.3 TXSTPE UPIENX.3 TXOUTI UPINTX.2 TXOUTE UPIENX.2 RXSTALLI UPINTX.1 RXSTALLE UPIENX.1 RXINI UPINTX.0 RXINE UPIENX.
Registers General USB Host Registers Table 132. UHCON Register UHCON (1.D9h) – USB Host General Control Register 7 6 5 4 3 2 1 0 - - - - - RESUME RESET SOFE Bit Number 7-3 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Send USB Resume 2 RESUME Set this bit to generate a USB Resume on the USB bus. Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Upstream Resume Received Interrupt 4 RXRSMI 3 RSMEDI 2 RSTI 1 DDISCI 0 DCONNI Set by hardware when an Upstream Resume has been received from the Device. Shall be cleared by software. Setting by software has no effect. Downstream Resume Sent Interrupt Set by hardware when a Downstream Resume has been sent to the Device. Shall be cleared by software. Setting by software has no effect.
Bit Number Bit Mnemonic Description Device Connection Interrupt Enable 0 DCONNE Set this bit to enable the DCONNI interrupt. Clear this bit to disable the DCONNI interrupt. Reset Value = 0000 0000b Table 135. UHADDR Register UHADDR (1.DBh) – USB Host Address Register 7 6 5 4 3 2 1 0 - HADDR6 HADDR5 HADDR4 HADDR3 HADDR2 HADDR1 HADDR0 Bit Number Bit Mnemonic Description 7 - 6-0 HADDR6:0 Reserved The value read from this bit is always 0. Do not set this bit.
AT85C51SND3Bx Table 137. UHFNUML Register UHFNUML (1.DDh) – USB Host Frame Number Low Register 7 6 5 4 3 2 1 0 FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0 Bit Number Bit Mnemonic Description Frame Number 7-0 FNUM7:0 The value contained in tis register is the current SOF number. This value can be modified by software. Reset Value = 0000 0000b Table 138. UHFLEN Register UHFLEN (1.
Table 140. UPRST Register UPRST (1.CAh) – USB Host Pipe Reset Register 7 6 5 4 3 2 1 0 - P6RST P5RST P4RST P3RST P2RST P1RST P0RST Bit Number Bit Mnemonic Description 7 - 6 P6RST 5 P5RST 4 P4RST 3 P3RST 2 P2RST 1 P1RST 0 P0RST Reserved The value read from this bit is always 0. Do not set this bit. Pipe 6 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 6. Pipe 5 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 5.
AT85C51SND3Bx Bit Number Bit Mnemonic Description IN Request mode 5 INMODE 4 AUTOSW 3 RSTDT 2 PNUMS 1 DFCRDY 0 PEN Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen. Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UINRQX register. Auto Switch Bank Set this bit to allow the auto switch bank mode for this Pipe. Clear this bit to otherwise.
Table 143. UPCFG1X Register UPCFG1X (1.CDh) – USB Pipe Configuration 1 Register 7 6 5 4 3 2 1 0 - PSIZE2 PSIZE1 PSIZE0 PBK1 PBK0 ALLOC - Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is always 0. Do not set this bit. Pipe Size 6-4 PSIZE2:0 Select the size of the Pipe: - 000: 8 - 001: 16 - 010: 32 - 011: 64 - 100: 128 - 101: 256 - 110: 512 - 111: 1024 Pipe Bank 3-2 PBK1:0 Select the number of bank to declare for the current Pipe.
AT85C51SND3Bx Table 145. UPSTAX Register UPSTAX (1.CEh) – USB Pipe Status Register 7 6 5 4 3 2 CFGOK OVERFI UNDERFI - DTSEQ1 DTSEQ0 Bit Number 1 0 NBUSYBK1 NBUSYBK0 Bit Mnemonic Description Configure Pipe Memory OK 7 CFGOK Set by hardware if the required memory configuration has been successfully performed. Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect on the configuration of the pipe.
Table 146. UPINRQX Register UPINRQX (1.DFh) – USB Pipe IN Number Of Request Register 7 6 5 4 3 2 1 0 INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 Bit Number Bit Mnemonic Description IN Request Number Before Freeze 7-0 INRQ7:0 Enter the number of IN transactions before the USB controller freezes the pipe. The USB controller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed.
AT85C51SND3Bx Table 148. UPINTX Register UPINTX (1.C8h) – USB Pipe Interrupt Register 7 6 5 4 3 2 1 0 FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI Bit Number Bit Mnemonic Description FIFO Control 7 FIFOCON For OUT and SETUP Pipe: Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP. Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
Bit Number Bit Mnemonic Description IN Data received 0 RXINI Set by hardware when a new USB message is stored in the current bank of the Pipe. This triggers an interrupt if the RXINE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. Reset Value = 0000 0000b Table 149. UPIENX Register UPIENX (1.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Pipe Data Bits 7-0 PDAT7:0 Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM. Reset Value = 0000 0000b Table 151. UPBCHX Register UPBCHX (1.D4h) – USB Pipe Data Counter High Register 7 6 5 4 3 2 1 0 - - - - - PBYCT10 PBYCT9 PBYCT8 Bit Number 7-3 2-0 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Byte count (high) Bits PBYCT10:8 Set by hardware.
Table 153. UPINT Register UPINT (1.D6h) – USB Pipe IN Number Of Request Register 7 6 5 4 3 2 1 0 - PINT6 PINT5 PINT4 PINT3 PINT2 PINT1 PINT0 Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is always 0. Do not set this bit. Pipe Interrupts Bits 6-0 PINT6:0 Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding endpoint interrupt enable bit is set. Cleared by hardware when the interrupt source is served.
AT85C51SND3Bx Audio Controller The Audio Controller embedded in AT85C51SND3Bx is based on four functional blocks detailed in the following sections: • The Clock Generator • The Audio Processor • The Audio Codec • The Audio DAC Interface Figure 69.
Figure 71. Audio Processor Block Diagram Audio Buffer CPU Digital Audio Processor Audio DAC Interface Baseband Processor CPU/DFC Audio Codec Audio Buffer The audio buffer receives the audio data flow coming from DFC or the C51. It is based on 1 Kbyte of dual-port RAM. Buffer Description The audio buffer can be accessed in read or write mode by both C51 and DFC. Access selection is done by the ABACC bit in APCON1.
AT85C51SND3Bx In order to avoid any spurious interrupts on the CPU side when a data transfer with the data flow controller is established, APREQE and APRDYE must be left cleared. Digital Audio Processor The digital audio processor is based on a proprietary digital signal processor.
Digital Volume Control The digital volume is controlled separately on right and left channel by setting the DVR4:0 and DVL4:0 bits respectively in APRDVOL and APLDVOL according to Table 154. Table 154.
AT85C51SND3Bx Mixing Mode A mixing mode can be established by setting MIXEN bit in AUCON. It consists in mixing the ADC output coming from microphone or line-in inputs with the output coming from the audio processor before feeding the internal or external audio DAC. Signal Clipping When volume controls (global + equalizer + bass boost) leads to signal saturation, output signal is clipped and ACLIPI flag is set in APINT. In such case, strategy to reduce volume is under user’s firmware responsibility.
Audio Codec The audio codec is controlled by four registers as detailed in Figure 74: Figure 74. Audio Codec Block Diagram ACORG.4:0 AORG4:0 D 1 A OUTR 0 From Audio Processor AODRV D ACCON.2 1 A OUTL 0 AOLG4:0 ACOLG.4:0 AOSSEL AILPG ACCON.1 ACIPG.3 AT 8 5 C 5 1S N D 3 B 2 & LINR Σ D 1 MICIN MICBIAS A 0 LINL AISSEL AIPG2:0 ACCON.4 ACIPG.2:0 To Audio Processor Bias Generator AMBEN AMBVS ACCON.5 ACCON.
AT85C51SND3Bx Table 157.
AIPG2:0 Gain Value 001 Line Inputs Preamplifier Gain +6 dB AIPG2:0 011 Gain Value +18 dB AIPG2:0 ≥ 101 Gain Value Reserved In AT85C51SND3B2 & AT85C51SND3B3, when Line Inputs are selected as output source (e.g. FM decoder playback) two preamplifier gain values can be applied by setting or clearing AILPG bit in ACIPG according to Table 161. Table 161.
AT85C51SND3Bx Figure 75. Audio DAC Interface Block Diagram OCLK AUD CLOCK DCLK Clock Controller 0 DSEL ADIEN 1 ADICON0.0 OVERS1:0 DSIZE ADICON0.2:1 ADICON0.3 CSPOL ADICON0.4 Data Converter Audio Data From Audio Processor DDAT JUST4:0 ADICON1.4:0 Clock Controller As soon as audio DAC interface is enabled by setting ADIEN bit in ADICON0, the master clock generated by the clock generator (see Section “Clock Generator”) is output on the OCLK pin which is the DAC over-sampling clock.
Figure 77. Audio Output Format DSEL DCLK DDAT Left Channel 1 2 3 Right Channel 13 14 15 LSB MSB B14 16 B1 1 2 3 13 14 15 LSB MSB B14 16 B1 I2S Format with DSIZE = 0 and JUST4:0 = 00001. DSEL DCLK Left Channel 1 DDAT 2 Right Channel 3 17 MSB B14 LSB 18 32 1 2 3 17 MSB B14 18 32 LSB I2S Format with DSIZE = 1 and JUST4:0 = 00001.
AT85C51SND3Bx Bit Number Bit Mnemonic Description 2-1 - 0 ACCKEN Reserved The value read from these bits is always 0. Do not set these bits. Audio Controller Clock Enable Bit Set to enable the Audio Controller Clock. Clear to disable the Audio Controller Clock. Reset Value = 0000 0000b Table 166. APCON0 Register APCON0 (1.
Bit Number Bit Mnemonic Description Audio Processor Load Enable Bit 1 APLOAD 0 DAPEN Set to enable audio processor codec code update. Clear to disable audio processor codec code update. Digital Audio Processor Enable Bit Set to enable the digital audio processor. Clear to disable the digital audio processor. Reset Value = 0000 0000b Table 168. APSTA Register APSTA (1.
AT85C51SND3Bx Table 170. APIEN Register APIEN (1.E9h) – Audio Processor Interrupt Enable Register 7 6 5 4 3 2 1 0 APGPE3 APGPE2 APGPE1 APGPE0 APEVTE ACLIPE APRDYE APREQE Bit Number 7-4 Bit Mnemonic Description Audio Processor General Purpose Interrupt Enable Bits APGPE3:0 Set to enable the audio processor general purpose interrupt. Clear to disable the audio processor general purpose interrupt.
Table 173. APTIM2 Register APTIM2 (2.C9h) – Audio Processor Timer Register 2 7 6 5 4 3 2 1 0 APT23 APT22 APT21 APT20 APT19 APT18 APT17 APT16 Bit Number 7-0 Bit Mnemonic Description APT23:16 Audio Processor Timer Most Significant Byte. Reset Value = 0000 0000b Table 174. APRDVOL, APLDVOL, APBDVOL, APMDVOL, APTDVOL Registers APRDVOL, APLDVOL, APBDVOL, APMDVOL, APTDVOL (2.F1h, 2.F2h, 2.F3h, 2.F4h, 2.
AT85C51SND3Bx Table 176. APELEV Register APELEV (2.F7h) - Audio Processor Equalizer Level Status Register 7 6 5 4 3 2 1 0 - - - EQLEV4 EQLEV3 EQLEV2 EQLEV1 EQLEV0 Bit Number Bit Mnemonic Description 7-5 - 4-0 EQLEV4:0 Reserved The value read from these bits is always 0. Do not set these bits. Equalizer Audio Level 00000b: min. level to 11111b: max. level. Reset Value = 0000 0000b Table 177. ACCON Register ACCON (2.
Bit Number Bit Mnemonic Description AT85C51SND3B2 and AT85C51SND3B3: Audio Output Enable Bit 0 AOEN - Set to enable the audio output system. Clear to disable the audio output system. AT85C51SND3B1: Reserved The value read from this bit is always 0. Do not set this bit. Reset Value = 0000 0000b Table 178. ACAUX Register (AT85C51SND3B2 and AT85C51SND3B3 only) ACAUX (2.
AT85C51SND3Bx Table 180. ACOLG Register (AT85C51SND3B2 and AT85C51SND3B3 only) ACOLG (2.ECh) – Audio Codec Left Output Gain Register 7 6 5 4 3 2 1 0 - - - AOLG4 AOLG3 AOLG2 AOLG1 AOLG0 Bit Number Bit Mnemonic Description 7-5 - 4-0 AOLG4:0 Reserved The value read from these bits is always 0. Do not set these bits. Audio Output Left Gain Refer to Table 157 for gain value. Reset Value = 0000 0000b Table 181. ACIPG Register ACIPG (2.
Bit Number Bit Mnemonic Description 1-2 OVERS1:0 0 ADIEN Audio Oversampling Ratio Bits Refer to Table 164 for bits description. Audio DAC Interface Enable Bit Set to enable the audio DAC interface. Clear to disable the audio DAC interface. Reset Value = 0000 0000b Table 183. ADICON1 Register ADICON1 (2.
AT85C51SND3Bx Table 186. ASSTA1 Register ASSTA1 (2.E3h) – Audio Stream Status Register 1 7 6 5 4 3 2 1 0 AS1S7 AS1S6 AS1S5 AS1S4 AS1S3 AS1S2 AS1S1 AS1S0 Bit Number 7-0 Bit Mnemonic Description AS1S7:0 Audio Stream Status Byte 1 Bits content depends on the audio codec firmware. Reset Value = 0000 0000b Table 187. ASSTA2 Register ASSTA2 (2.
Nand Flash Controller The AT85C51SND3Bx implement a hardware Nand Flash Controller (NFC) embedding the following features: • Up to 4 Nand Flash (NF) memories • SMC/XD support with up to 3 NF memories • 512-byte, 1024-byte, 2048-byte page size support (provision for up to 8192-byte page size) • Hardware ECC support • High speed: up to 35 ns cycle time NF support • Functional overview Two separated secured memory segments: – application segment for user codes, audio codec codes, fonts, screens…
AT85C51SND3Bx Figure 79. Nand Flash Connection IOVDD NFCLE CLE NFALE ALE NFWE WE NFRE RE NFD7:0 VDD ALE WP RE VSS WP 0 NFCE3:0 WE NF2 RE D7:0 CE VSS WP 1 VDD CLE ALE WE NF1 D7:0 CE VDD CLE ALE WE NF0 D7:0 NFWP VDD CLE RE NF3 SMC D7:0 CE VSS 2 WP CE VSS 3 IOVSS Clock Unit The NFC clock is generated based on the clock generator as detailed in Section "DFC/NFC Clock Generator", page 30.
Table 189. NFPGCFG / SMPGCFG Registers NFPGCFG / SMPGCFG – NF / SMC Device Page Configuration Registers 7 6 5 4 3 2 1 0 NDB3 NDB2 NDB1 NDB0 NDB4 - - - Bit Number Bit Mnemonic Description 7-3 NDB4:0 2-0 - Page Data Number Number of data bytes in a page (unit is 512 bytes). Reserved The value read from these bits is always 0. Do not set these bits. Reset Value = 0000 0000b Table 190.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Block Size Bits 1-0 BSIZE1:0 Write following value to specify the number of pages per block. This information is needed by the controller for the block protection management. 0 0: 32 pages per block 0 1: 64 pages per block 1 0: 128 pages per block 1 1: 256 pages per block Reset Value = 0000 0000b Specific Action As soon as the NFC is configured, the NFC is ‘idle’, i.e. ready for operation and its running status flag NFRUN in NFSTA is cleared.
Table 193. Device Selection Allowed Configuration SMCEN NUMDEV Allowed DEV Comment 0 0 1 0, 1 2 0, 1, 2 3 0, 1, 2, 3 0 3 (SMC) 1 3 (SMC), 0 2 3 (SMC), 0, 1 The SMLCK signal can not be used in this configuration, the SMLCK bit is irrelevant. 3 3 (SMC), 0, 1, 2 Neither SMLCK nor SMINS signals can be used in this configuration. SMCD and SMLCK bits have an irrelevant value. SMCTE shall be cleared.
AT85C51SND3Bx Note that it is not possible to reset A9:8 after each command (write in NFCMD): the device status read command is used after opening a page (for read) to poll the busy status. Command Sending Writing a command in NFCMD generates the following cycles: Assembly code: mov direct, # NFCLK / 2 NFCEx NFCLE NFALE NFWE NFRE NFD[7:0] Command A write in that register re-initializes the ECC engine and the ECC FIFO. A read in that register returns an unexpected value.
Data Reading/Writing The NFDAT and NFDATF registers allow reading or writing of a byte without the use of the DFC as detailed in the Section “Data Unit”. It launches an immediate read or write NF cycle, depending if the software reads or writes in those registers. Note: • The ECC is also computed when byte are read or written via NFDAT or NFDATF. A write in NFDAT or NFDATF will produce an immediate “write cycle” (the NF signals will be asserted accordingly) to store the byte given by the CPU.
AT85C51SND3Bx Assembly code: mov #, direct NFCLK / 2 NFCEx NFCLE NFALE NFWE NFRE NFD[7:0] Read data, TRS cleared CPU: 40 ns setup, timing [1.5; 0.5] [15;30] ns hold NFCEx NFCLE NFALE NFWE NFRE NFD[7:0] Read data, TRS set CPU: 40 ns setup Timing [1; 1] [15;30] ns hold • A read of NFDAT returns to the CPU the byte contained in that register, but does not launch an extra background “read cycle”.
Figure 80. Nand Flash Read Example manual return in dum dum OK ACT read mode my my CMD NFD NFD CMD ADC ADR ADR CED ADR CMD NFD NFD NFD NFD NFD NFD NFD CMD CED ACT ifc CPU Dev 70h ATF ATF 00h C R1 R2 =0 R3 70h ATF ATF ATF ATF ATF ATF ATF 00h =1 (R) ACT End of page OK CED Must be held low during Tr Ready RE Tr Data zone Spare zone (Check ECC; etc...) BUSYD auto Check Legend: • “ifc CPU” illustrates the commands given by the CPU to the NFC.
AT85C51SND3Bx Table 195. Spare Zone Content Offset 0-1 Description User Data Area. Shall be managed by software. 2 ECC Valid. Managed by NFC. 3 User Data Byte. Managed by NFC through NFUDAT register. 4 Data Status Flag. Shall be managed by software. 5 Block Status Flag. Shall be managed by software. 6-7 Logical Block Address. Managed by NFC through NFLOG register (see Section “Logical Block Address”). 8-10 ECC Area-2. Managed by NFC. 11-12 Logical Block Address.
Spare Zone Mode 1 SPZEN ECCEN ECCRDYE Description 0 1 0 1 0 X Not Supported This configuration is reserved and must not be programmed. Not Supported This configuration is reserved and must not be programmed. The spare zone is not managed by the NFC. The data zone is contiguous. The user sends the commands to prepare the page for read or write. The data flow starts when the READ or WRITE bits are set by the user (write in NFACT).
AT85C51SND3Bx • Logical Block Address read the ECC FIFO, (keeping the ECCs in memory), re-initialize it, resume the data transfer, and to write all the ECC bytes at the end of the page. In order to automatically and properly fill the spare zone, the logical block address must be provided to the NFC. This is done by writing a 2-bytes descriptor byte by byte to the NFLOG register according to Table 197. The first byte written is byte 0.
Write Protection The NFC provides a hardware mechanism to protect full or part of the memory against any spurious writing. This is achieved by using the NFWP signal and connecting it to the WP pins of the memories.
AT85C51SND3Bx Figure 81. Nand Flash Write Protection Scheme Block 0 Block 0 FPB LPB Block 0 protected FPB protected LPB protected LPB FPB protected FPB < LPB FPB > LPB FPB = LPB Default Since the NFWP signal state is part of the device status, the user can detect a fault be reading it. ECC Error Management When an ECC error is detected, the ECCERRI flag is set in NFINT and the 4-byte ECC error FIFO is updated.
Bit Number 7-0 Bit Mnemonic Description 0 Reserved The value read from these bits is always 0. Second Half Error Id Flag Id of the error in the second “256-byte” group of the sector. SHERRID1-0 1: Correctable error. 2: Not correctable error. 3: Not correctable error in the ECC. Anyway, the data is good. 3-2 First Half Error Id Flag Id of the error in the first “256-byte” group of the sector. FHERRID1-0 1: Correctable error. 2: Not correctable error. 3: Not correctable error in the ECC.
AT85C51SND3Bx Card Lock Input As shown in Figure 83 the SMLCK (SMC/XD Lock) input implements an internal pull-up, in order to provide static high level when card is not present in the socket. SMLCK level is reported by SMLCK bit(1) in NFSTA register. Note: 1. SDWP bit is not relevant until SMC management is enabled and a card is present in the socket (SMCD = 0). Figure 83. Card Write Protection Input Block Diagram IOVDD RPU SMLCK SMLCK NFSTA.
• or illegal operation (ILGLI) – Attempt to access a NF device which is not declared (e.g. DEV= 4 while NUMDEV= 2) – Write of events (NFDATF, NFDAT, NFCMD, NFADC, NFADR) while NFC is running (NFRUN= 1). Note that writing in NFACT while NFC is running (RUN=1) does not lead to an ILGLI interrupt. As so on as an ena bled interrupt is triggered, the NFC becomes not running (NFRUN= 0). Registers Table 202. NFCFG Register NFCFG (1.
AT85C51SND3Bx Table 204. NFCON Register NFCON (1.9Bh) – Nand Flash Controller Control Register 7 6 5 4 3 2 1 0 - - - TRS NFWP SPZEN ECCEN NFEN Bit Number Bit Mnemonic Description 7-5 - 4 TRS 3 NFWP 2 SPZEN 1 ECCEN 0 NFEN Reserved The value read from these bits is always 0. Do not set these bits. Timing Read Select Bit Set to use timing [1; 1] for read cycle. Clear to use timing [1.5; 0.5] for read cycle.
Table 207. NFADC Register NFADC (1.9Eh) – Nand-Flash Controller Column Address Register 7 6 5 4 3 2 1 0 NFCAD7 NFCAD6 NFCAD5 NFCAD4 NFCAD3 NFCAD2 NFCAD1 NFCAD0 Bit Number 7-0 Bit Mnemonic Description NFCAD7:0 Column Address Byte Reset Value = 0000 0000b A read of that register returns an unexpected value. Table 208. NFCMD Register NFCMD (1.
AT85C51SND3Bx Table 210. NFDAT Register NFDAT (1.A2h) – Nand-Flash Controller Data Access Register 7 6 5 4 3 2 1 0 DATD7 DATD6 DATD5 DATD4 DATD3 DATD2 DATD1 DATD0 Bit Number Bit Mnemonic Description Data Byte 7-0 DATD7:0 Writing data sends a data to the currently selected NF. Reading data gets the data returned by the last read cycle. Reset Value = 0000 0000b Table 211. NFDATF Register NFDATF (1.
Bit Number Bit Mnemonic Description Running Flag 0 NFRUN Set by hardware to signal that it is currently running. Cleared by hardware to signal it is not running. Reset Value = 0000 0000b Table 213. NFECC Register NFECC (1.A4h) – Nand Flash Controller ECC 1 and ECC 2 Register 7 6 5 4 3 2 1 0 NFED7 NFED6 NFED5 NFED4 NFED3 NFED2 NFED1 NFED0 Bit Number Bit Mnemonic Description Nand Flash ECC 6-byte Data FIFO 7-0 NFED7:0 Read Mode Sequential reading returns 2 ECC values of 3 bytes.
AT85C51SND3Bx Table 215. NFIEN Register NFIEN (1.A6h) – Nand Flash Controller Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - SMCTE ILGLE ECCRDYE ECCERRE STOPE Bit Number Bit Mnemonic Description 7-5 - 4 SMCTE 3 ILGLE Reserved The value read from these bits is always 0. Do not set these bits. SMC Transition Interrupt Enable Bit Set to enable the SMCTI interrupt. Clear to disable the SMCTI interrupt. Illegal Operation Interrupt Enable Bit Set to enable the ILGLI interrupt.
Table 217. NFBPH Register NFUDAT (1.94h) – Nand Flash Controller Byte Position (MSB) Register 7 6 5 4 3 2 1 0 BP15 BP14 BP13 BP12 BP11 BP10 BP9 BP8 Bit Number 7-0 Bit Mnemonic Description BP15:8 Nand Flash Position High Byte Most significant byte of the Byte Position counter. Reset Value = 0000 0000b Table 218. NFBPL Register NFUDAT (1.
AT85C51SND3Bx MMC/SD Controller The AT85C51SND3Bx embed a MMC/SD controller allowing connecting of MMC and SD cards in 1-bit or 4-bit modes. For MMC, 4-bit mode rely on the MMC Specification V4.0.
tion from the card through the SDCMD line. These channels are detailed in the following sections. Figure 87. Command Line Controller Block Diagram TX Pointer CTPTR MMCON0.4 17-Byte FIFO MMCMD Write Data Converter // -> Serial CRC7 Generator TX COMMAND Line Finished State Machine MMINT.5 EOCI TXCEN Command Transmitter RX Pointer CRPTR MMCON0.5 17-Byte FIFO MMCMD Read SDCMD MMCON1.0 Data Converter Serial -> // MMSTA.2 MMSTA.
AT85C51SND3Bx Figure 88. Command Transmission Flow Command Transmission Configure Response RXCEN = X RFMT = X CRCDIS = X Load Command in Buffer MMCMD = index MMCMD = argument Transmit Command TXCEN = 1 Command Receiver The end of the response reception is signalled by the EORI flag in MMINT register. This flag may generate an interrupt request as detailed in Section “Interrupt”.
Data Line Controller As shown in Figure 89, the data line controller is based on a 16-Byte FIFO used both by the data transmitter channel and by the data receiver channel. Data transfer can be handled in transmission or received by the Data Flow Controller (see Section “Data Flow Controller”, page 78) or by the C51 using MMDAT register. Figure 89. Data Line Controller Block Diagram MMINT.3 MMSTA.1 MMSTA.3 MMSTA.
AT85C51SND3Bx Data Configuration Before sending or receiving any data, the data line controller must be configured according to the type of the data transfer considered. This is achieved using the Data Format bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format while setting DFMT bit enables the data block format.
Data Transmission Transmission is enabled by setting DATEN bit in MMCON1 register. FIFO must be filled after this flag is set. If at least the FIFO is half full, data is transmitted immediately when the response to the write command has already been received, or is delayed after the reception of the response if its status is correct. In both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition.
AT85C51SND3Bx Figure 91.
Figure 92. Data Block Transmission Flows Data Block Transmission Data Block Initialization Data Block Transmission ISR Start Transmission DATEN = 1 Start Transmission DATEN = 1 FIFO Filling write 16 data to MMDAT Unmask FIFO Empty HFRM = 0 FIFO Empty? HFRI = 1? FIFO Filling write 8 data to MMDAT FIFO Filling write 16 data to MMDAT FIFO Empty? HFRS = 1? No More Data To Send? FIFO Filling write 8 data to MMDAT No More Data To Send? Mask FIFO Empty HFRM = 1 b. Interrupt mode a.
AT85C51SND3Bx from such situation. In case of time-out, the data controller and its internal state machine may be reset by setting and clearing the DCR bit in MMCON2 register. This time-out may be disarmed after receiving 8 data (HFRS flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). DFC Data Reading In case the data transfer is handled by the DFC, a DFC channel must be configured with the MMC controller as source peripheral.
Figure 94. Data Block Reception Flows Data Block Reception Data Block Initialization Data Block Reception ISR Start Transmission DATEN = 1 Unmask FIFO Full HFRM = 0 Start Reception DATEN = 1 FIFO Full? HFRI = 1? FIFO Reading read 8 data from MMDAT FIFO Full? HFRS = 1? No More Data To Receive? FIFO Reading read 8 data from MMDAT Mask FIFO Full HFRM = 1 No More Data To Receive? a. Polling mode b.
AT85C51SND3Bx Figure 96. SD Card Write Protection Input Block Diagram IOVDD RPU SDLCK SDWP MMSTA.7 Interrupt As shown in Figure 97, the MMC controller implements eight interrupt sources reported in CDETI, EORI, EOCI, EOFI, WFRI, HFRI and EOBI flags in MMCINT register. These flags are detailed in the previous sections. All these sources are maskable separately using CDETM, EORM, EOCM, EOFM, WFRM, HFRM and EOBM mask bits respectively in MMMSK register.
Registers Table 221. MMCON0 Register MMCON0 (1.B1h) – MMC Control Register 0 7 6 5 4 3 2 1 0 - DPTRR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7 - 6 DPTRR 5 CRPTR 4 CTPTR 3 MBLOCK 2 DFMT 1 RFMT 0 CRCDIS Reserved The value read from this bit is always 0. do not set this bit Data Pointer Reset Bit Set to reset the read and write pointer of the data FIFO. Cleared by hardware after pointer reset is achieved.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Data Transfer Enable Bit 2 DATEN 1 RXCEN 0 TXCEN Set to enable data transmission or reception immediately or after response has been received. Cleared by hardware after the CRC reception in reception mode or after the busy status if any in transmission mode. Response Command Enable Bit Set to enable the reception of a response following a command transmission. Cleared by hardware when response is received.
Bit Number 7-0 Bit Mnemonic Description BLEN7:0 Block Length LSB Refer to Table 220 for byte description Reset Value = 0000 0000b Table 225. MMSTA Register MMSTA (1.B5h Read Only) – MMC Status Register 7 6 5 4 3 2 1 0 SDWP CDET CBUSY CRC16S DATFS CRC7S WFRS HFRS Bit Number Bit Mnemonic Description SD Card Write Protect Bit 7 SDWP 6 CDET 5 CBUSY Set by hardware when the SD card socket WP switch is opened. Cleared by hardware when the SD card socket WP switch is closed.
AT85C51SND3Bx Table 226. MMINT Register MMINT (1.BEh Read Only) – MMC Interrupt Register 7 6 5 4 3 2 1 0 CDETI EORI EOCI EOFI WFRI HFRI EOBI - Bit Number Bit Mnemonic Description Card Detection Interrupt Flag 7 CDETI 6 EORI 5 EOCI 4 EOFI Set by hardware every time CDET bit in MMSTA is toggling. Cleared when reading MMINT. End of Response Interrupt Flag Set by hardware at the end of response reception. Cleared when reading MMINT.
Bit Number Bit Mnemonic Description End Of Response Interrupt Mask Bit 6 EORM 5 EOCM 4 EOFM 3 WFRM 2 HFRM 1 EOBM 0 - Set to prevent EORI flag from generating an interrupt. Clear to allow EORI flag to generate an interrupt. End Of Command Interrupt Mask Bit Set to prevent EOCI flag from generating an interrupt. Clear to allow EOCI flag to generate an interrupt. End Of Frame Interrupt Mask Bit Set to prevent EOFI flag from generating an interrupt.
AT85C51SND3Bx Parallel Slave Interface The AT85C51SND3Bx implement a Parallel Slave Interface (PSI) allowing parallel connection with a host for remote control and data transfer. By using this interface, the AT85C51SND3Bx can be seen as a multimedia co-processor and be remotely controlled by the host.
PSI Addressing The AT85C51SND3Bx are accessible by a host in read or write at two different address locations by setting or clearing the SA0 address signal. The data management is detailed in following sections and differs depending on SA0 level. Table 234 shows the addressing truth table. Figure 100 and Figure 101 show the read and write host cycles. Table 230. PSI Addressing Truth Table SA0 SRD / SWR Selection 1 Read Host reads the PSISTH register to get PSI status from both hardware and software.
AT85C51SND3Bx Figure 102. Write Data Sampling Configuration PER CLK SCS SWR Write Data SD7:0 Data Sampling PSWS2:0 “SA0= H” Mode 0 1 2 3 4 5 6 7 The “SA0= H” mode is particularly fitting control management over a protocol. Figure 103 shows a data cycle from host to device. Prior to send any data bytes, the host must take care of the PSI state by reading the AT85C51SND3Bx with SA0 signal set. This returns PSISTH: the host status register content.
Host can then read or write by burst an amount of data defined by the protocol (see Section “Data Flow Controller”, page 78). In order to avoid any underrun or overrun condition during burst transfer, host must be slower than the DFC destination peripheral (host write) or the DFC source peripheral (host read). Overrun - Underrun Conditions An overrun condition occurs when the hosts writes data quicker than the slave can consume it.
AT85C51SND3Bx Registers Table 231. PSICON Register PSICON (1.ADh) – PSI Control Register 7 6 5 4 3 2 1 0 PSEN PSBSYE PSRUNE PSWS2 PSWS1 PSWS0 - - Bit Number Bit Mnemonic Description Interface Enable Bit 7 PSEN 6 PSBSYE 5 PSRUNE 4-2 PSWS2:0 1-0 - Set to enable the PSI controller. Clear to disable the PSI controller. Busy Interrupt Enable Bit Set to enable the busy interrupt. Clear to disable the busy interrupt.
Bit Number 3-0 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not set these bits. Reset Value = 1000 0000b Table 233. PSISTH Register PSISTH (1.ACh) – PSI Host Status Register 7 6 5 4 3 2 1 0 PSHBSY PSSTH6 PSSTH5 PSSTH4 PSSTH3 PSSTH2 PSSTH1 PSSTH0 Bit Number Bit Mnemonic Description Interface Busy Flag 7 PSHBSY 6-0 PSSTH6:0 Host Access (Read with SA0 = H) Copy of the PSBSY flag. Software Access Always returned as logic 0.
AT85C51SND3Bx Serial I/O Port The AT85C51SND3Bx implement a Serial Input/Output Port (SIO) allowing serial communication. By using this interface, the AT85C51SND3B can be seen as a multimedia co-processor and be remotely controlled by the host.
Figure 106. SIO Block Diagram Baud Rate Generator SIO CLOCK RXD Receiver CPU Bus DFC Bus Character Format RTS Interrupt Controller SIO Interrupt Request Transmitter TXD CTS The character consists of five fields: start, data, parity, stop and guard fields. Figure 107 shows a character example with 8 data bits, 1 parity bit, 2 stop bits and 2 guard bits. Figure 107.
AT85C51SND3Bx Table 238. Stop Bit Number Selection STOP Guard Field Description 0 1 Stop Bit. 1 2 Stop Bits. The guard field is not part of a character and is an optional inter-character spacing composed of 0 to 3 bits transmitted at high level by programming GBIT1:0 bits in SCON according to Table 239. The guard field allows transmitter to be compliant with connected host (overrun avoiding) and is emitted after the last stop bit of a character. Table 239.
Figure 109. Baud Rate Generator Block Diagram Integer SIO CLOCK Fractional ÷C Pre-Divider To serial Receiver & Transmitter A÷B Post-Divider CDIV7:0 ADIV7:0 BDIV7:0 SBRG0 SBRG1 SBRG2 SBRG CLOCK Table 240. Baud Rate Generator Value (12x oversampling) Baud Rate FSIO = 16 MHz B C ε% 125 6 5 0 110 99 125 0 19200 125 12 5 0 125 9 5 38400 125 24 5 0 125 18 57600 125 36 5 0 115200 125 72 5 0 FSIO = 120 MHz (1) ε% 124 5 7 0.007 125 3 5 0 110 15 142 0.033 0 124 10 7 0.
AT85C51SND3Bx Receiver As shown in Figure 110, the receiver is based on a character handler taking care of character integrity check and feeding the reception shift register filling itself a 16-byte data FIFO managed by the FIFO and flow controller. Figure 110. Receiver Block Diagram SBUF Rx 16-byte FIFO FIFO & Flow Controller RTS RI RTSEN RTSTH1:0 SINT.0 SCON.2 SCON.1:0 Rx Shift Reg Character Handler BRG CLOCK RXD OVERSF3:0 SFCON.7:4 Flow Control OEI PEI FEI SINT.4 SINT.3 SINT.
Receiver Errors There are three kinds of errors that can be set during character reception: the framing error, the parity error, and the overrun error detailed in the following sections. Framing Error A framing error occurs when the stop field of a received character is not at high level. Framing error is reported in FEI flag in SINT. Framing error condition is acknowledged by clearing the FEI flag.
AT85C51SND3Bx Figure 113. SIO Controller Interrupt System RI SINT.0 RIE SIEN.0 TI SINT.1 TIE SIEN.1 FEI SINT.2 SIO Interrupt Request FEIE SIEN.2 PEI ES SINT.3 IEN0.4 PEIE SIEN.3 OEI SINT.4 OEIE SIEN.4 EOTI SINT.5 EOTIE SIEN.5 Registers Table 242. SCON Register SCON (0.
Table 243. SFCON Register SFCON (0.95h) – SIO Flow Control Register 7 6 5 4 3 2 1 0 OVRSF3 OVRSF2 OVRSF1 OVRSF0 CTSEN RTSEN RTSTH1 RTSTH0 Bit Number 7-4 Bit Mnemonic Description Over Sampling Factor Bits OVRSF3:0 Number of time a data bit is sampled for level determination. Oversampling factor = OVRSF3:0 + 1. Clear To send Enable Bit 3 CTSEN 2 RTSEN 1-0 RTSTH1:0 Set to enable transmission hardware flow control using CTS signal. Clear to disable transmission hardware flow control.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Transmission Interrupt Flag 1 TI Set by hardware when the Tx FIFO is not full: a character can be loaded through SBUF. Cleared by hardware when the Tx FIFO becomes full: no more character can be loaded. Reception Interrupt Flag 0 RI Set by hardware when the Rx FIFO is not empty: character ready to be read through SBUF. Cleared by hardware when the Rx FIFO becomes empty: no more character to be read. Reset Value = 0X10 0010b Table 245.
Table 246. SBUF Register SBUF (1.AAh) – SIO Data Buffer Register 7 6 5 4 3 2 1 0 SIOD7 SIOD6 SIOD5 SIOD4 SIOD3 SIOD2 SIOD1 SIOD0 Bit Number 7-0 Bit Mnemonic Description SIOD7:0 8-Bit data Buffer. Reset Value = XXXX XXXXb Table 247. SBRG0 Register SBRG0 (0.92h) – SIO Baud Rate Generator Register 0 7 6 5 4 3 2 1 0 CDIV7 CDIV6 CDIV5 CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 Bit Number 7-0 Bit Mnemonic Description CDIV7:0 Baud Rate Generator 8-bit C divider.
AT85C51SND3Bx Serial Peripheral Interface The AT85C51SND3Bx implement a Synchronous Peripheral Interface (SPI) allowing full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
Figure 115. Typical Slave SPI Bus Configuration SS SSn SS1 SS0 MASTER SS SO SS Slave 1 SI SCK SO Slave 2 AT85C51SND3B Slave SI MISO MOSI SCK SCK MISO MOSI SCK Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 251); SPSCR, the SPI status and control register (see Table 252); and SPDAT, the SPI data register (see Table 253).
AT85C51SND3Bx The transmission begins by writing to SPDAT through CPU or DFC. Writing to SPDAT writes to an intermediate register which is automatically loaded to the shift register if no transmission is in progress. Reading SPDAT through CPU or DFC reads an intermediate register updated at the end of each transfer. The byte begins shifting out on the MOSI pin under the control of the bit rate generator. This generator also controls the shift register of the slave peripheral through the SCK output pin.
When the AT85C51SND3Bx is the only slave on the bus, it can be useful not to use SS pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect when CPHA is cleared (see Section "SS Management", page 227). Figure 118. SPI Slave Mode Block Diagram MISO/P3.0 SPDAT WR MOSI/P3.1 I SCK/P3.2 Q 8-bit Shift Register MODF CPU or DFC Bus SPSCR.2 UARTM SPDAT RD SPSCR.4 OVR Control and Clock Logic SS/P3.3 SPSCR.6 SPIF SPSCR.7 SSDIS SPTE SPCON.
AT85C51SND3Bx Data Transfer The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled and the edges on which the output data are shifted (see Figure 119 and Figure 120). For simplicity, Figure 119 and Figure 120 depict the SPI waveforms in idealized form and do not provide precise timing information. For timing parameters refer to the Section “AC Characteristics”, page 246.
Figure 120 shows a SPI transmission with CPHA = 1, where the first SCK edge is used by the slave as a start of transmission signal. Therefore, SS may remain asserted between each byte transmission (see Figure 121). This format may be preferred in systems having only one master and only one slave driving the MISO data line. Figure 121.
AT85C51SND3Bx – the MSTR bit in SPCON is cleared Clearing the MODF bit is accomplished by reading SPSCR with MODF bit set, followed by a write to SPCON. SPI controller may be re-enabled (SPEN = 1) after the MODF bit is cleared. Figure 123.
OverRun Condition This error means that the speed is not adapted for the running application. An OverRun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. The last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. Therefore, an overrun error always indicates the loss of data.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Master Mode Select 4 MSTR 3 CPOL 2 CPHA 1-0 SPR1:0 Set to select the master mode. Clear to select the slave mode. SPI Clock Polarity Bit Set to have the clock output set to high level in idle state. Clear to have the clock output set to low level in idle state. SPI Clock Phase Bit Set to have the data sampled when the clock returns to idle state (see CPOL). Clear to have the data sampled when the clock leaves the idle state (see CPOL).
Bit Number Bit Mnemonic Description SPTE Interrupt Enable Bit 1 SPTEIE Set to enable SPTE interrupt generation. Clear to disable SPTE interrupt generation. MODF Interrupt Enable Bit 0 MODFIE Set and cleared by software: - Set to enable MODF interrupt generation - Clear to disable MODF interrupt generation Reset Value = 0000 1000b Table 253.
AT85C51SND3Bx Display Interface The AT85C51SND3Bx implement a display interface allowing glueless direct interfacing (thanks to its highly configurable capability) to almost all of the LCD controllers found in either graphic or text LCD display. These LCD controllers interface is from either 6800 or 8080 compatible type with some variant in the implementation.
Access Cycles The AT85C51SND3Bx enables connection of LCD controller with normalized 6800 and 8080 interface as shown in Figure 127 and Figure 128, but also enables connection of LCD controller with non normalized 6800 and 8080 interface as shown in Figure 129 and Figure 130. This is achieved by setting or clearing CYCT bit in LCDCON1 for selecting non normalized or normalized access type. Figure 127. 6800 Normalized Type Access Cycle CS, RW, RS E ADSUH ACCW ADSUH Figure 128.
AT85C51SND3Bx Sleep Wait Time The sleep wait time is the time between two consecutive access cycle. It can be programmed by SLW1:0 bits in LCDCON1 from 1 oscillator clock period up to 4 oscillator clock periods Full Access Cycle Time The full access cycle time can be computed by adding the address set-up time, the access width time, the address hold time and the sleep wait time. However, some LCD controller may require that the inactive state of the selection signal being equal to the access width time.
Registers Table 255. LCDCON0 Register LCDCON0 (1.96h) – LCD Control Register 0 7 6 5 4 3 2 1 0 BUINV LCIFS ADSUH1 ADSUH0 ACCW3 ACCW2 ACCW1 ACCW0 Bit Number Bit Mnemonic Description Busy Invert Active 7 BUINV 6 LCIFS 5-4 ADSUH1:0 Set to check busy bits selected in LCDBUM as active low. Clear to check busy bits selected in LCDBUM as active high. Interface Select Bit Set to select 6800 interface type. Clear to select 8080 interface type.
AT85C51SND3Bx Bit Number Bit Mnemonic Description Cycle Type Selection 3 LCYCT 2 LCEN 1 LCRD Set to select non normalized access cycles (6800 or 8080 interface). Clear to select normalized access cycles (6800 or 8080 interface). LCD Interface Enable Set to enable the LCD Interface. Clear to disable the LCD Interface. LCD Read Command Set to initiate a read data or status register from LCD controller. Cleared by hardware at the end of read.
Table 259. LCDDAT Register LCDDAT (1.97h) – LCD Data Register 7 6 5 4 3 2 1 0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Bit Number 7:0 Bit Mnemonic Description LD7:0 LCD Data Byte Reading a data automatically initiates a new read cycle to the LCD controller.
AT85C51SND3Bx Keyboard Interface The AT85C51SND3Bx implement a keyboard interface allowing the connection of a 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.
Registers Table 260. KBCON Register KBCON (0.A3h) – Keyboard Control Register 7 6 5 4 3 2 1 0 KINL3 KINL2 KINL1 KINL0 KINM3 KINM2 KINM1 KINM0 Bit Number Bit Mnemonic Description Keyboard Input Level Bit 7-4 KINL3:0 3-0 KINM3:0 Set to enable a high level detection on the respective KIN3:0 input. Clear to enable a low level detection on the respective KIN3:0 input. Keyboard Input Mask Bit Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
Electrical Characteristics Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to V SS .................................... -0.3 *NOTICE: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. to +4.0 V IOL per I/O Pin ..
AT85C51SND3Bx Oscillator & Crystal Schematic Figure 134. Crystal Connection X1 C1 Q C2 APVSS Note: Parameters X2 For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). Table 258. Oscillator & Crystal Characteristics VDD = 1.65 to 3.
Parameters Table 259. DC-DC Filter Characteristics TA = -40 to +85°C Symbol Parameter Min Typ Max Unit LDC DC-DC Inductance 10 µH CDC1 Low ESR Decoupling Capacitor 20 µF CDC2 Low ESR Decoupling Capacitor 100 nF Table 260. DC-DC Power Characteristics VBAT = 0.9 to 3.6 V; TA = -40 to +85°C Symbol Parameter Min VBAT DC-DC Input Voltage 0.9 VDC DC-DC Output Voltage 1.6 IDC DC-DC Output Current HMAX Maximum Efficiency 1.75 Max Unit 3.6 V IDC = 40 mA 1.
AT85C51SND3Bx Table 263. Low Voltage Regulator Power Characteristics HVDD = 3 to 3.6 V; TA = -40 to +85°C Symbol Parameter VLV Low Voltage Regulator Output Voltage ILV Low Voltage Regulator Output Current Min Typ Max Unit 1.7 1.8 1.9 V 50 mA Test Conditions IDC = 50 mA USB Schematic Figure 137. USB Connection RUB UVCC VBUS UBIAS RUFT D+ CUB RUFT DPF DMF D- DPH UID ID UVSS DMH GND VSS Parameters Table 264.
Parameters Table 265. Audio Codec Components Characteristics TA = -40 to +85°C Symbol Parameter Min Typ Max Unit (1) 100 0.1(2) µF LINR/LINL DC-Decoupling Capacitor 1 µF CINM MICIN DC-Decoupling Capacitor 1 µF CVCM AVCM Filter Capacitor 100 nF CAREF AREF Filter Capacitor 1 µF MICBIAS Filter Capacitor 10 nF COUT OUTR/OUTL DC-Decoupling Capacitor CINL CMB Notes: 1. Value in low impedance mode (Headphone mode when AODRV = 1) 2.
AT85C51SND3Bx AC Characteristics NFC Interface Definition of Symbols Table 1. NFC Interface Timing Symbol Definitions Signals Timings Conditions D NFD7:0 In H High O NFD7:0 Out L Low R NFRE V Valid W NFWE X No Longer Valid E NFCEn Z Floating A NFALE C NFCLE Table 267. NFC Interface AC timings VDD = 1.65 to 3.
Waveforms Figure 140. NFC Command Latch Cycle Waveforms TELWH TWHEH TCHWH TWHCL NFCEn NFCLE TWLWH NFWE NFALE TOVWH NFD7:0 TWHOX Command Figure 141. NFC Address Latch Cycle Waveforms TELWH TWHEH NFCEn NFCLE TWLWH NFWE TAHWH TWHAL NFALE TOVWH NFD7:0 TWHOX Col Add Figure 142.
AT85C51SND3Bx Figure 143. NFC Write Cycle Waveforms TELWH TWHEH NFCEn NFCLE NFALE TWLWH NFWE TOVWH NFD7:0 TWHOX Data MMC Interface Definition of symbols Table 268. MMC Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Table 269. MMC Interface AC timings VDD = 1.65 to 3.
Waveforms Figure 144. MMC Input-Output Waveforms TCHCH TCHCX TCLCX MCLK TCHCL TCLCH TCHIX TIVCH MCMD Input MDAT Input TCHOX TOVCH MCMD Output MDAT Output LCD Interface To be defined Definition of Symbols Timings Waveforms SIO Interface To be defined Definition of Symbols Timings Waveforms SPI Interface Definition of Symbols Table 270.
AT85C51SND3Bx Table 271. SPI Interface Master AC Timing VDD = 1.65 to 3.6 V; TA = -40 to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 2 TPER TCHCX Clock High Time 0.8 TPER TCLCX Clock Low Time 0.
Waveforms Figure 145. SPI Slave Waveforms (SSCPHA= 0) SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) TCHCH TCHCX TCLSH TCHSH TCLCH TSHSL TCLCX TCHCL SCK (SSCPOL= 1) (input) MISO (output) TCLOX TCHOX TCLOV TCHOV TSLOV SLAVE MSB OUT BIT 6 TSHOX SLAVE LSB OUT (1) TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 146.
AT85C51SND3Bx Figure 147. SPI Master Waveforms (SSCPHA= 0) SS (output) TCHCH SCK (SSCPOL= 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOX TCHOX TCLOV TCHOV MISO (output) Note: Port Data MSB OUT BIT 6 LSB OUT Port Data SS handled by software using general purpose port pin. Figure 148.
Audio DAC Interface Definition of symbols Table 272. Audio DAC Interface Timing Symbol Definitions Signals Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Table 273. Audio Interface AC timings Timings VDD = 1.65 to 3.
AT85C51SND3Bx Timings Table 275. External Clock AC Timings VDD = 1.65 to 3.6 V; TA = -40 to +85°C Symbol Parameter Max Unit TCLCL Clock Period 38 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns Cyclic Ratio in X2 mode 40 TCR Waveforms Min 60 % Figure 150.
AT85C51SND3Bx Ordering Information Table 280. Ordering Information Part Number Temp.
Package Information LQFP 100 254 AT85C51SND3Bx 7632A–MP3–03/06
AT85C51SND3Bx CTBGA 100 255 7632A–MP3–03/06
Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Key Features ......................................................................................... 2 Block Diagram ...................................................................................... 3 Application Information ..............................................
Registers..............................................................................................................59 Timers/Counters ................................................................................. 65 Timer/Counter Operations .................................................................................. 65 Timer Clock Controller ........................................................................................ 65 Timer 0.......................................................
AT85C51SND3A Power-On and Reset ........................................................................................ 101 Speed Identification .......................................................................................... 101 Endpoint Reset ................................................................................................. 102 USB Reset ........................................................................................................ 102 Endpoint Selection.................
Clock Unit ......................................................................................................... Control Unit....................................................................................................... Data Unit........................................................................................................... End of Data Transfer ........................................................................................ Security Unit ......................................
AT85C51SND3A AC Characteristics ............................................................................................. 246 Ordering Information........................................................................ 253 Package Information ........................................................................ 254 LQFP 100 ......................................................................................................... 254 CTBGA 100 ..........................................................
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