Datasheet

4341H–MP3–10/07

AT8xC51SND2C/MP3B

15.1.10 Register

Table 15-11. AUXCON Register

AUXCON (S:90h) – Auxiliary Control Register

Reset Value = 1111 1111b

Table 15-12. Dac Control Register Register - DAC_CTRL (00h)

7 6 5 4 3 2 1 0

SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0

Bit

Number Bit Mnemonic Description

7 SDA

TWI Serial Data

SDA is the bidirectional Two Wire data line.

6 SCL

TWI Serial Clock

When TWI controller is in master mode, SCL outputs the serial clock to the slave

peripherals. When TWI controller is in slave mode, SCL receives clock from the master

controller.

5 - Not used.

4 AUDCDOUT Audio Dac SPI Data Output.

3 AUDCDIN Audio Dac SPI Data Input

2 AUDCCLK Audio Dac SPI clock

1 AUDCCS

Audio Dac Chip select

Set to deselect DAC

Clear to select DAC

0 KIN0 Keyboard Input Interrupt.

7 6 5 4 3 2 1 0

ONPADRV ONAUXIN ONDACR ONDACL ONLNOR ONLNOL ONLNIR ONLNIL

Bit

Number

Bit

Mnemonic

Description

7 ONPADRV

Differential mono PA driver