Datasheet

85
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 15-7. Dac SPI Interface
15.1.4 DAC Interface SPI Protocol
On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read
operation. The 7 following bits are used for the register address and the 8 last ones are the write
data. For both address and data, the most significant bit is the first one.
In case of a read operation, AUDCDOUT provides the contents of the read register, MSB first.
The transfer is enabled by the AUDCCS signal active low. The interface is resetted at every ris-
ing edge of AUDCCS in order to come back to an idle state, even if the transfer does not
succeed. The DAC Interface SPI is synchronized with the serial clock AUDCCLK. Falling edge
latches AUDCDIN input and rising edge shifts AUDCDOUT output bits.
Note that the DLCK must run during any DAC SPI interface access (read or write).
Figure 15-8. DAC SPI Interface Timings
rw
a6
a5
a4
a3
a2
a1
d7
d6
d5
d3
d7
d6
d5
d4
d1
d0
d2
d3
d0
d1
d2
d4
a0
AUDCDOUT
AUDCDIN
AUDCCLK
AUDCCS
Thsdi
Tssen
Tc
Twl
Twh
Thsen
Tssdi
AUDCDOUT
AUDCDIN
AUDCCLK
Tdsdo
Thsdo
AUDCCS