Datasheet

80
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 14-6. AUDDAT Register
AUDDAT (S:9Dh) – Audio Interface Data Register
Reset Value = 1111 1111b
Table 14-7. AUDCLK Register
AUDCLK (S:ECh) – Audio Clock Divider Register
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
AUD7 AUD6 AUD5 AUD4 AUD3 AUD2 AUD1 AUD0
Bit Number
Bit
Mnemonic Description
7 - 0 AUD7:0
Audio Data
8-bit sampling data for voice or sound playing.
7 6 5 4 3 2 1 0
- - - AUCD4 AUCD3 AUCD2 AUCD1 AUCD0
Bit Number
Bit
Mnemonic Description
7 - 5 -
Reserved
The value read from these bits is always 0. Do not set these bits.
4 - 0 AUCD4:0
Audio Clock Divider
5-bit divider for audio clock generation.