Datasheet

78
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 14-6. MP3 Mode Audio Configuration Flow
14.8 Registers
Table 14-3. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
Reset Value = 0000 1000b
Table 14-4. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
MP3 Mode
Configuration
Configure Interface
HLR = X
DSIZ = X
POL = X
JUST4:0 = XXXXXb
SRC = 0
Program Audio Clock
Enable DAC System
Clock
AUDEN = 1
Wait For
DAC Set-up Time
Enable Data Request
DRQEN = 1
7 6 5 4 3 2 1 0
JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR
Bit Number
Bit
Mnemonic Description
7 - 3 JUST4:0
Audio Stream Justification Bits
Refer to Section "Data Converter", page 75 for bits description.
2 POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I
2
S mode).
1 DSIZ
Audio Data Size
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
0 HLR
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
7 6 5 4 3 2 1 0
SRC DRQEN MSREQ MUDRN - DUP1 DUP0 AUDEN
Bit Number
Bit
Mnemonic Description
7 SRC
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.