Datasheet

73
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 13-14. MP3TRE Register
MP3TRE (S:B6h) – MP3 Treble Control Register
Reset Value = 0000 0000b
Table 13-15. MP3CLK Register
MP3CLK (S:EBh) – MP3 Clock Divider Register
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
- - - TRE4 TRE3 TRE2 TRE1 TRE0
Bit Number
Bit
Mnemonic Description
7 - 5 -
Reserved
The value read from these bits is always 0. Do not set these bits.
4-0 TRE4:0
Treble Gain Value
Refer to Table 13-3 for the treble control description.
7 6 5 4 3 2 1 0
- - - MPCD4 MPCD3 MPCD2 MPCD1 MPCD0
Bit Number
Bit
Mnemonic Description
7 - 5 -
Reserved
The value read from these bits is always 0. Do not set these bits.
4-0 MPCD4:0
MP3 Decoder Clock Divider
5-bit divider for MP3 decoder clock generation.